src/mem/cache/blk.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /** @file
  32  * Definitions of a simple cache block class.
  33  */
  34
  35 #ifndef __CACHE_BLK_HH__
  36 #define __CACHE_BLK_HH__
  37
  38 #include <list>
  39
  40 #include "base/printable.hh"
  41 #include "sim/core.hh"          // for Tick
  42 #include "arch/isa_traits.hh"   // for Addr
  43 #include "mem/packet.hh"
  44 #include "mem/request.hh"
  45
  46 /**
  47  * Cache block status bit assignments
  48  */
  49 enum CacheBlkStatusBits {
  50     /** valid, readable */
  51     BlkValid =          0x01,
  52     /** write permission */
  53     BlkWritable =       0x02,
  54     /** read permission (yes, block can be valid but not readable) */
  55     BlkReadable =       0x04,
  56     /** dirty (modified) */
  57     BlkDirty =          0x08,
  58     /** block was referenced */
  59     BlkReferenced =     0x10,
  60     /** block was a hardware prefetch yet unaccessed*/
  61     BlkHWPrefetched =   0x20
  62 };
  63
  64 /**
  65  * A Basic Cache block.
  66  * Contains the tag, status, and a pointer to data.
  67  */
  68 class CacheBlk
  69 {
  70   public:
  71     /** The address space ID of this block. */
  72     int asid;
  73     /** Data block tag value. */
  74     Addr tag;
  75     /**
  76      * Contains a copy of the data in this block for easy access. This is used
  77      * for efficient execution when the data could be actually stored in
  78      * another format (COW, compressed, sub-blocked, etc). In all cases the
  79      * data stored here should be kept consistant with the actual data
  80      * referenced by this block.
  81      */
  82     uint8_t *data;
  83     /** the number of bytes stored in this block. */
  84     int size;
  85
  86     /** block state: OR of CacheBlkStatusBit */
  87     typedef unsigned State;
  88
  89     /** The current status of this block. @sa CacheBlockStatusBits */
  90     State status;
  91
  92     /** Which curTick will this block be accessable */
  93     Tick whenReady;
  94
  95     /**
  96      * The set this block belongs to.
  97      * @todo Move this into subclasses when we fix CacheTags to use them.
  98      */
  99     int set;
 100
 101     /** Number of references to this block since it was brought in. */
 102     int refCount;
 103
 104   protected:
 105     /**
 106      * Represents that the indicated thread context has a "lock" on
 107      * the block, in the LL/SC sense.
 108      */
 109     class Lock {
 110       public:
 111         int contextId;     // locking context
 112
 113         // check for matching execution context
 114         bool matchesContext(Request *req)
 115         {
 116             return (contextId == req->contextId());
 117         }
 118
 119         Lock(Request *req)
 120             : contextId(req->contextId())
 121         {
 122         }
 123     };
 124
 125     /** List of thread contexts that have performed a load-locked (LL)
 126      * on the block since the last store. */
 127     std::list<Lock> lockList;
 128
 129   public:
 130
 131     CacheBlk()
 132         : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 133           set(-1), refCount(0)
 134     {}
 135
 136     /**
 137      * Copy the state of the given block into this one.
 138      * @param rhs The block to copy.
 139      * @return a const reference to this block.
 140      */
 141     const CacheBlk& operator=(const CacheBlk& rhs)
 142     {
 143         asid = rhs.asid;
 144         tag = rhs.tag;
 145         data = rhs.data;
 146         size = rhs.size;
 147         status = rhs.status;
 148         whenReady = rhs.whenReady;
 149         set = rhs.set;
 150         refCount = rhs.refCount;
 151         return *this;
 152     }
 153
 154     /**
 155      * Checks the write permissions of this block.
 156      * @return True if the block is writable.
 157      */
 158     bool isWritable() const
 159     {
 160         const int needed_bits = BlkWritable | BlkValid;
 161         return (status & needed_bits) == needed_bits;
 162     }
 163
 164     /**
 165      * Checks the read permissions of this block.  Note that a block
 166      * can be valid but not readable if there is an outstanding write
 167      * upgrade miss.
 168      * @return True if the block is readable.
 169      */
 170     bool isReadable() const
 171     {
 172         const int needed_bits = BlkReadable | BlkValid;
 173         return (status & needed_bits) == needed_bits;
 174     }
 175
 176     /**
 177      * Checks that a block is valid.
 178      * @return True if the block is valid.
 179      */
 180     bool isValid() const
 181     {
 182         return (status & BlkValid) != 0;
 183     }
 184
 185     /**
 186      * Check to see if a block has been written.
 187      * @return True if the block is dirty.
 188      */
 189     bool isDirty() const
 190     {
 191         return (status & BlkDirty) != 0;
 192     }
 193
 194     /**
 195      * Check if this block has been referenced.
 196      * @return True if the block has been referenced.
 197      */
 198     bool isReferenced() const
 199     {
 200         return (status & BlkReferenced) != 0;
 201     }
 202
 203     /**
 204      * Check if this block was the result of a hardware prefetch, yet to
 205      * be touched.
 206      * @return True if the block was a hardware prefetch, unaccesed.
 207      */
 208     bool wasPrefetched() const
 209     {
 210         return (status & BlkHWPrefetched) != 0;
 211     }
 212
 213     /**
 214      * Track the fact that a local locked was issued to the block.  If
 215      * multiple LLs get issued from the same context we could have
 216      * redundant records on the list, but that's OK, as they'll all
 217      * get blown away at the next store.
 218      */
 219     void trackLoadLocked(PacketPtr pkt)
 220     {
 221         assert(pkt->isLLSC());
 222         lockList.push_front(Lock(pkt->req));
 223     }
 224
 225     /**
 226      * Clear the list of valid load locks.  Should be called whenever
 227      * block is written to or invalidated.
 228      */
 229     void clearLoadLocks() { lockList.clear(); }
 230
 231     /**
 232      * Handle interaction of load-locked operations and stores.
 233      * @return True if write should proceed, false otherwise.  Returns
 234      * false only in the case of a failed store conditional.
 235      */
 236     bool checkWrite(PacketPtr pkt)
 237     {
 238         Request *req = pkt->req;
 239         if (pkt->isLLSC()) {
 240             // it's a store conditional... have to check for matching
 241             // load locked.
 242             bool success = false;
 243
 244             for (std::list<Lock>::iterator i = lockList.begin();
 245                  i != lockList.end(); ++i)
 246             {
 247                 if (i->matchesContext(req)) {
 248                     // it's a store conditional, and as far as the memory
 249                     // system can tell, the requesting context's lock is
 250                     // still valid.
 251                     success = true;
 252                     break;
 253                 }
 254             }
 255
 256             req->setExtraData(success ? 1 : 0);
 257             clearLoadLocks();
 258             return success;
 259         } else {
 260             // for *all* stores (conditional or otherwise) we have to
 261             // clear the list of load-locks as they're all invalid now.
 262             clearLoadLocks();
 263             return true;
 264         }
 265     }
 266 };
 267
 268 /**
 269  * Simple class to provide virtual print() method on cache blocks
 270  * without allocating a vtable pointer for every single cache block.
 271  * Just wrap the CacheBlk object in an instance of this before passing
 272  * to a function that requires a Printable object.
 273  */
 274 class CacheBlkPrintWrapper : public Printable
 275 {
 276     CacheBlk *blk;
 277   public:
 278     CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
 279     virtual ~CacheBlkPrintWrapper() {}
 280     void print(std::ostream &o, int verbosity = 0,
 281                const std::string &prefix = "") const;
 282 };
 283
 284
 285
 286 #endif //__CACHE_BLK_HH__