src/mem/cache/blk.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /** @file
  32  * Definitions of a simple cache block class.
  33  */
  34
  35 #ifndef __CACHE_BLK_HH__
  36 #define __CACHE_BLK_HH__
  37
  38 #include <list>
  39
  40 #include "base/printable.hh"
  41 #include "mem/packet.hh"
  42 #include "mem/request.hh"
  43 #include "sim/core.hh"          // for Tick
  44
  45 /**
  46  * Cache block status bit assignments
  47  */
  48 enum CacheBlkStatusBits {
  49     /** valid, readable */
  50     BlkValid =          0x01,
  51     /** write permission */
  52     BlkWritable =       0x02,
  53     /** read permission (yes, block can be valid but not readable) */
  54     BlkReadable =       0x04,
  55     /** dirty (modified) */
  56     BlkDirty =          0x08,
  57     /** block was referenced */
  58     BlkReferenced =     0x10,
  59     /** block was a hardware prefetch yet unaccessed*/
  60     BlkHWPrefetched =   0x20
  61 };
  62
  63 /**
  64  * A Basic Cache block.
  65  * Contains the tag, status, and a pointer to data.
  66  */
  67 class CacheBlk
  68 {
  69   public:
  70     /** The address space ID of this block. */
  71     int asid;
  72     /** Data block tag value. */
  73     Addr tag;
  74     /**
  75      * Contains a copy of the data in this block for easy access. This is used
  76      * for efficient execution when the data could be actually stored in
  77      * another format (COW, compressed, sub-blocked, etc). In all cases the
  78      * data stored here should be kept consistant with the actual data
  79      * referenced by this block.
  80      */
  81     uint8_t *data;
  82     /** the number of bytes stored in this block. */
  83     int size;
  84
  85     /** block state: OR of CacheBlkStatusBit */
  86     typedef unsigned State;
  87
  88     /** The current status of this block. @sa CacheBlockStatusBits */
  89     State status;
  90
  91     /** Which curTick() will this block be accessable */
  92     Tick whenReady;
  93
  94     /**
  95      * The set this block belongs to.
  96      * @todo Move this into subclasses when we fix CacheTags to use them.
  97      */
  98     int set;
  99
 100     /** whether this block has been touched */
 101     bool isTouched;
 102
 103     /** Number of references to this block since it was brought in. */
 104     int refCount;
 105
 106     /** holds the context source ID of the requestor for this block. */
 107     int contextSrc;
 108
 109   protected:
 110     /**
 111      * Represents that the indicated thread context has a "lock" on
 112      * the block, in the LL/SC sense.
 113      */
 114     class Lock {
 115       public:
 116         int contextId;     // locking context
 117
 118         // check for matching execution context
 119         bool matchesContext(Request *req)
 120         {
 121             return (contextId == req->contextId());
 122         }
 123
 124         Lock(Request *req)
 125             : contextId(req->contextId())
 126         {
 127         }
 128     };
 129
 130     /** List of thread contexts that have performed a load-locked (LL)
 131      * on the block since the last store. */
 132     std::list<Lock> lockList;
 133
 134   public:
 135
 136     CacheBlk()
 137         : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 138           set(-1), isTouched(false), refCount(0), contextSrc(-1)
 139     {}
 140
 141     /**
 142      * Copy the state of the given block into this one.
 143      * @param rhs The block to copy.
 144      * @return a const reference to this block.
 145      */
 146     const CacheBlk& operator=(const CacheBlk& rhs)
 147     {
 148         asid = rhs.asid;
 149         tag = rhs.tag;
 150         data = rhs.data;
 151         size = rhs.size;
 152         status = rhs.status;
 153         whenReady = rhs.whenReady;
 154         set = rhs.set;
 155         refCount = rhs.refCount;
 156         return *this;
 157     }
 158
 159     /**
 160      * Checks the write permissions of this block.
 161      * @return True if the block is writable.
 162      */
 163     bool isWritable() const
 164     {
 165         const State needed_bits = BlkWritable | BlkValid;
 166         return (status & needed_bits) == needed_bits;
 167     }
 168
 169     /**
 170      * Checks the read permissions of this block.  Note that a block
 171      * can be valid but not readable if there is an outstanding write
 172      * upgrade miss.
 173      * @return True if the block is readable.
 174      */
 175     bool isReadable() const
 176     {
 177         const State needed_bits = BlkReadable | BlkValid;
 178         return (status & needed_bits) == needed_bits;
 179     }
 180
 181     /**
 182      * Checks that a block is valid.
 183      * @return True if the block is valid.
 184      */
 185     bool isValid() const
 186     {
 187         return (status & BlkValid) != 0;
 188     }
 189
 190     /**
 191      * Check to see if a block has been written.
 192      * @return True if the block is dirty.
 193      */
 194     bool isDirty() const
 195     {
 196         return (status & BlkDirty) != 0;
 197     }
 198
 199     /**
 200      * Check if this block has been referenced.
 201      * @return True if the block has been referenced.
 202      */
 203     bool isReferenced() const
 204     {
 205         return (status & BlkReferenced) != 0;
 206     }
 207
 208     /**
 209      * Check if this block was the result of a hardware prefetch, yet to
 210      * be touched.
 211      * @return True if the block was a hardware prefetch, unaccesed.
 212      */
 213     bool wasPrefetched() const
 214     {
 215         return (status & BlkHWPrefetched) != 0;
 216     }
 217
 218     /**
 219      * Track the fact that a local locked was issued to the block.  If
 220      * multiple LLs get issued from the same context we could have
 221      * redundant records on the list, but that's OK, as they'll all
 222      * get blown away at the next store.
 223      */
 224     void trackLoadLocked(PacketPtr pkt)
 225     {
 226         assert(pkt->isLLSC());
 227         lockList.push_front(Lock(pkt->req));
 228     }
 229
 230     /**
 231      * Clear the list of valid load locks.  Should be called whenever
 232      * block is written to or invalidated.
 233      */
 234     void clearLoadLocks() { lockList.clear(); }
 235
 236     /**
 237      * Handle interaction of load-locked operations and stores.
 238      * @return True if write should proceed, false otherwise.  Returns
 239      * false only in the case of a failed store conditional.
 240      */
 241     bool checkWrite(PacketPtr pkt)
 242     {
 243         Request *req = pkt->req;
 244         if (pkt->isLLSC()) {
 245             // it's a store conditional... have to check for matching
 246             // load locked.
 247             bool success = false;
 248
 249             for (std::list<Lock>::iterator i = lockList.begin();
 250                  i != lockList.end(); ++i)
 251             {
 252                 if (i->matchesContext(req)) {
 253                     // it's a store conditional, and as far as the memory
 254                     // system can tell, the requesting context's lock is
 255                     // still valid.
 256                     success = true;
 257                     break;
 258                 }
 259             }
 260
 261             req->setExtraData(success ? 1 : 0);
 262             clearLoadLocks();
 263             return success;
 264         } else {
 265             // for *all* stores (conditional or otherwise) we have to
 266             // clear the list of load-locks as they're all invalid now.
 267             clearLoadLocks();
 268             return true;
 269         }
 270     }
 271 };
 272
 273 /**
 274  * Simple class to provide virtual print() method on cache blocks
 275  * without allocating a vtable pointer for every single cache block.
 276  * Just wrap the CacheBlk object in an instance of this before passing
 277  * to a function that requires a Printable object.
 278  */
 279 class CacheBlkPrintWrapper : public Printable
 280 {
 281     CacheBlk *blk;
 282   public:
 283     CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
 284     virtual ~CacheBlkPrintWrapper() {}
 285     void print(std::ostream &o, int verbosity = 0,
 286                const std::string &prefix = "") const;
 287 };
 288
 289
 290
 291 #endif //__CACHE_BLK_HH__