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40 * Authors: Erik Hallnor
45 * Definitions of a simple cache block class.
48 #ifndef __MEM_CACHE_BLK_HH__
49 #define __MEM_CACHE_BLK_HH__
57 #include "base/printable.hh"
58 #include "base/types.hh"
59 #include "mem/cache/replacement_policies/base.hh"
60 #include "mem/packet.hh"
61 #include "mem/request.hh"
64 * Cache block status bit assignments
66 enum CacheBlkStatusBits : unsigned {
67 /** valid, readable */
69 /** write permission */
71 /** read permission (yes, block can be valid but not readable) */
73 /** dirty (modified) */
75 /** block was a hardware prefetch yet unaccessed*/
76 BlkHWPrefetched = 0x20,
77 /** block holds data from the secure memory space */
82 * A Basic Cache block.
83 * Contains the tag, status, and a pointer to data.
85 class CacheBlk : public ReplaceableEntry
88 /** Task Id associated with this block */
91 /** Data block tag value. */
94 * Contains a copy of the data in this block for easy access. This is used
95 * for efficient execution when the data could be actually stored in
96 * another format (COW, compressed, sub-blocked, etc). In all cases the
97 * data stored here should be kept consistant with the actual data
98 * referenced by this block.
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
105 /** The current status of this block. @sa CacheBlockStatusBits */
108 /** Which curTick() will this block be accessible */
112 * The set and way this block belongs to.
113 * @todo Move this into subclasses when we fix CacheTags to use them.
117 /** Number of references to this block since it was brought in. */
120 /** holds the source requestor ID for this block. */
123 /** Tick on which the block was inserted in the cache. */
128 * Represents that the indicated thread context has a "lock" on
129 * the block, in the LL/SC sense.
133 ContextID contextId; // locking context
134 Addr lowAddr; // low address of lock range
135 Addr highAddr; // high address of lock range
137 // check for matching execution context, and an address that
138 // is within the lock
139 bool matches(const RequestPtr &req) const
141 Addr req_low = req->getPaddr();
142 Addr req_high = req_low + req->getSize() -1;
143 return (contextId == req->contextId()) &&
144 (req_low >= lowAddr) && (req_high <= highAddr);
147 // check if a request is intersecting and thus invalidating the lock
148 bool intersects(const RequestPtr &req) const
150 Addr req_low = req->getPaddr();
151 Addr req_high = req_low + req->getSize() - 1;
153 return (req_low <= highAddr) && (req_high >= lowAddr);
156 Lock(const RequestPtr &req)
157 : contextId(req->contextId()),
158 lowAddr(req->getPaddr()),
159 highAddr(lowAddr + req->getSize() - 1)
164 /** List of thread contexts that have performed a load-locked (LL)
165 * on the block since the last store. */
166 std::list<Lock> lockList;
169 CacheBlk() : data(nullptr)
174 CacheBlk(const CacheBlk&) = delete;
175 CacheBlk& operator=(const CacheBlk&) = delete;
176 virtual ~CacheBlk() {};
179 * Checks the write permissions of this block.
180 * @return True if the block is writable.
182 bool isWritable() const
184 const State needed_bits = BlkWritable | BlkValid;
185 return (status & needed_bits) == needed_bits;
189 * Checks the read permissions of this block. Note that a block
190 * can be valid but not readable if there is an outstanding write
192 * @return True if the block is readable.
194 bool isReadable() const
196 const State needed_bits = BlkReadable | BlkValid;
197 return (status & needed_bits) == needed_bits;
201 * Checks that a block is valid.
202 * @return True if the block is valid.
206 return (status & BlkValid) != 0;
210 * Invalidate the block and clear all state.
212 virtual void invalidate()
215 task_id = ContextSwitchTaskId::Unknown;
219 srcMasterId = Request::invldMasterId;
220 tickInserted = MaxTick;
225 * Check to see if a block has been written.
226 * @return True if the block is dirty.
230 return (status & BlkDirty) != 0;
234 * Check if this block was the result of a hardware prefetch, yet to
236 * @return True if the block was a hardware prefetch, unaccesed.
238 bool wasPrefetched() const
240 return (status & BlkHWPrefetched) != 0;
244 * Check if this block holds data from the secure memory space.
245 * @return True if the block holds data from the secure memory space.
247 bool isSecure() const
249 return (status & BlkSecure) != 0;
253 * Set member variables when a block insertion occurs. Resets reference
254 * count to 1 (the insertion counts as a reference), and touch block if
255 * it hadn't been touched previously. Sets the insertion tick to the
256 * current tick. Does not make block valid.
258 * @param tag Block address tag.
259 * @param is_secure Whether the block is in secure space or not.
260 * @param src_master_ID The source requestor ID.
261 * @param task_ID The new task ID.
263 virtual void insert(const Addr tag, const bool is_secure,
264 const int src_master_ID, const uint32_t task_ID);
267 * Track the fact that a local locked was issued to the
268 * block. Invalidate any previous LL to the same address.
270 void trackLoadLocked(PacketPtr pkt)
272 assert(pkt->isLLSC());
273 auto l = lockList.begin();
274 while (l != lockList.end()) {
275 if (l->intersects(pkt->req))
276 l = lockList.erase(l);
281 lockList.emplace_front(pkt->req);
285 * Clear the any load lock that intersect the request, and is from
286 * a different context.
288 void clearLoadLocks(const RequestPtr &req)
290 auto l = lockList.begin();
291 while (l != lockList.end()) {
292 if (l->intersects(req) && l->contextId != req->contextId()) {
293 l = lockList.erase(l);
301 * Pretty-print a tag, and interpret state bits to readable form
302 * including mapping to a MOESI state.
304 * @return string with basic state information
306 std::string print() const
314 * state writable dirty valid
321 * Note that only one cache ever has a block in Modified or
322 * Owned state, i.e., only one cache owns the block, or
323 * equivalently has the BlkDirty bit set. However, multiple
324 * caches on the same path to memory can have a block in the
325 * Exclusive state (despite the name). Exclusive means this
326 * cache has the only copy at this level of the hierarchy,
327 * i.e., there may be copies in caches above this cache (in
328 * various states), but there are no peers that have copies on
329 * this branch of the hierarchy, and no caches at or above
330 * this level on any other branch have copies either.
332 unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
335 case 0b111: s = 'M'; break;
336 case 0b011: s = 'O'; break;
337 case 0b101: s = 'E'; break;
338 case 0b001: s = 'S'; break;
339 case 0b000: s = 'I'; break;
340 default: s = 'T'; break; // @TODO add other types
342 return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
343 "dirty: %d tag: %x", status, s, isValid(),
344 isWritable(), isReadable(), isDirty(), tag);
348 * Handle interaction of load-locked operations and stores.
349 * @return True if write should proceed, false otherwise. Returns
350 * false only in the case of a failed store conditional.
352 bool checkWrite(PacketPtr pkt)
354 assert(pkt->isWrite());
357 if (!pkt->isLLSC() && lockList.empty())
360 const RequestPtr &req = pkt->req;
363 // it's a store conditional... have to check for matching
365 bool success = false;
367 auto l = lockList.begin();
368 while (!success && l != lockList.end()) {
369 if (l->matches(pkt->req)) {
370 // it's a store conditional, and as far as the
371 // memory system can tell, the requesting
372 // context's lock is still valid.
380 req->setExtraData(success ? 1 : 0);
381 // clear any intersected locks from other contexts (our LL
382 // should already have cleared them)
386 // a normal write, if there is any lock not from this
387 // context we clear the list, thus for a private cache we
388 // never clear locks on normal writes
396 * Special instance of CacheBlk for use with tempBlk that deals with its
397 * block address regeneration.
400 class TempCacheBlk final : public CacheBlk
404 * Copy of the block's address, used to regenerate tempBlock's address.
409 TempCacheBlk() : CacheBlk() {}
410 TempCacheBlk(const TempCacheBlk&) = delete;
411 TempCacheBlk& operator=(const TempCacheBlk&) = delete;
415 * Invalidate the block and clear all state.
417 void invalidate() override {
418 CacheBlk::invalidate();
424 * Set member variables when a block insertion occurs. A TempCacheBlk does
425 * not have all the information required to regenerate the block's address,
426 * so it is provided the address itself for easy regeneration.
428 * @param addr Block address.
429 * @param is_secure Whether the block is in secure space or not.
431 void insert(const Addr addr, const bool is_secure)
445 * Get block's address.
447 * @return addr Address value.
456 * Simple class to provide virtual print() method on cache blocks
457 * without allocating a vtable pointer for every single cache block.
458 * Just wrap the CacheBlk object in an instance of this before passing
459 * to a function that requires a Printable object.
461 class CacheBlkPrintWrapper : public Printable
465 CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
466 virtual ~CacheBlkPrintWrapper() {}
467 void print(std::ostream &o, int verbosity = 0,
468 const std::string &prefix = "") const;
471 #endif //__MEM_CACHE_BLK_HH__