src/mem/cache/blk.hh

   1 /*
   2  * Copyright (c) 2012-2017 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Andreas Sandberg
  42  */
  43
  44 /** @file
  45  * Definitions of a simple cache block class.
  46  */
  47
  48 #ifndef __MEM_CACHE_BLK_HH__
  49 #define __MEM_CACHE_BLK_HH__
  50
  51 #include <list>
  52
  53 #include "base/printable.hh"
  54 #include "mem/packet.hh"
  55 #include "mem/request.hh"
  56
  57 /**
  58  * Cache block status bit assignments
  59  */
  60 enum CacheBlkStatusBits : unsigned {
  61     /** valid, readable */
  62     BlkValid =          0x01,
  63     /** write permission */
  64     BlkWritable =       0x02,
  65     /** read permission (yes, block can be valid but not readable) */
  66     BlkReadable =       0x04,
  67     /** dirty (modified) */
  68     BlkDirty =          0x08,
  69     /** block was a hardware prefetch yet unaccessed*/
  70     BlkHWPrefetched =   0x20,
  71     /** block holds data from the secure memory space */
  72     BlkSecure =         0x40,
  73 };
  74
  75 /**
  76  * A Basic Cache block.
  77  * Contains the tag, status, and a pointer to data.
  78  */
  79 class CacheBlk
  80 {
  81   public:
  82     /** Task Id associated with this block */
  83     uint32_t task_id;
  84
  85     /** Data block tag value. */
  86     Addr tag;
  87     /**
  88      * Contains a copy of the data in this block for easy access. This is used
  89      * for efficient execution when the data could be actually stored in
  90      * another format (COW, compressed, sub-blocked, etc). In all cases the
  91      * data stored here should be kept consistant with the actual data
  92      * referenced by this block.
  93      */
  94     uint8_t *data;
  95
  96     /** block state: OR of CacheBlkStatusBit */
  97     typedef unsigned State;
  98
  99     /** The current status of this block. @sa CacheBlockStatusBits */
 100     State status;
 101
 102     /** Which curTick() will this block be accessable */
 103     Tick whenReady;
 104
 105     /**
 106      * The set and way this block belongs to.
 107      * @todo Move this into subclasses when we fix CacheTags to use them.
 108      */
 109     int set, way;
 110
 111     /** whether this block has been touched */
 112     bool isTouched;
 113
 114     /** Number of references to this block since it was brought in. */
 115     unsigned refCount;
 116
 117     /** holds the source requestor ID for this block. */
 118     int srcMasterId;
 119
 120     Tick tickInserted;
 121
 122   protected:
 123     /**
 124      * Represents that the indicated thread context has a "lock" on
 125      * the block, in the LL/SC sense.
 126      */
 127     class Lock {
 128       public:
 129         ContextID contextId;     // locking context
 130         Addr lowAddr;      // low address of lock range
 131         Addr highAddr;     // high address of lock range
 132
 133         // check for matching execution context, and an address that
 134         // is within the lock
 135         bool matches(const RequestPtr req) const
 136         {
 137             Addr req_low = req->getPaddr();
 138             Addr req_high = req_low + req->getSize() -1;
 139             return (contextId == req->contextId()) &&
 140                    (req_low >= lowAddr) && (req_high <= highAddr);
 141         }
 142
 143         // check if a request is intersecting and thus invalidating the lock
 144         bool intersects(const RequestPtr req) const
 145         {
 146             Addr req_low = req->getPaddr();
 147             Addr req_high = req_low + req->getSize() - 1;
 148
 149             return (req_low <= highAddr) && (req_high >= lowAddr);
 150         }
 151
 152         Lock(const RequestPtr req)
 153             : contextId(req->contextId()),
 154               lowAddr(req->getPaddr()),
 155               highAddr(lowAddr + req->getSize() - 1)
 156         {
 157         }
 158     };
 159
 160     /** List of thread contexts that have performed a load-locked (LL)
 161      * on the block since the last store. */
 162     std::list<Lock> lockList;
 163
 164   public:
 165
 166     CacheBlk()
 167     {
 168         invalidate();
 169     }
 170
 171     CacheBlk(const CacheBlk&) = delete;
 172     CacheBlk& operator=(const CacheBlk&) = delete;
 173     virtual ~CacheBlk() {};
 174
 175     /**
 176      * Checks the write permissions of this block.
 177      * @return True if the block is writable.
 178      */
 179     bool isWritable() const
 180     {
 181         const State needed_bits = BlkWritable | BlkValid;
 182         return (status & needed_bits) == needed_bits;
 183     }
 184
 185     /**
 186      * Checks the read permissions of this block.  Note that a block
 187      * can be valid but not readable if there is an outstanding write
 188      * upgrade miss.
 189      * @return True if the block is readable.
 190      */
 191     bool isReadable() const
 192     {
 193         const State needed_bits = BlkReadable | BlkValid;
 194         return (status & needed_bits) == needed_bits;
 195     }
 196
 197     /**
 198      * Checks that a block is valid.
 199      * @return True if the block is valid.
 200      */
 201     bool isValid() const
 202     {
 203         return (status & BlkValid) != 0;
 204     }
 205
 206     /**
 207      * Invalidate the block and clear all state.
 208      */
 209     virtual void invalidate()
 210     {
 211         tag = MaxAddr;
 212         task_id = ContextSwitchTaskId::Unknown;
 213         status = 0;
 214         whenReady = MaxTick;
 215         isTouched = false;
 216         refCount = 0;
 217         srcMasterId = Request::invldMasterId;
 218         tickInserted = MaxTick;
 219         lockList.clear();
 220     }
 221
 222     /**
 223      * Check to see if a block has been written.
 224      * @return True if the block is dirty.
 225      */
 226     bool isDirty() const
 227     {
 228         return (status & BlkDirty) != 0;
 229     }
 230
 231     /**
 232      * Check if this block was the result of a hardware prefetch, yet to
 233      * be touched.
 234      * @return True if the block was a hardware prefetch, unaccesed.
 235      */
 236     bool wasPrefetched() const
 237     {
 238         return (status & BlkHWPrefetched) != 0;
 239     }
 240
 241     /**
 242      * Check if this block holds data from the secure memory space.
 243      * @return True if the block holds data from the secure memory space.
 244      */
 245     bool isSecure() const
 246     {
 247         return (status & BlkSecure) != 0;
 248     }
 249
 250     /**
 251      * Track the fact that a local locked was issued to the
 252      * block. Invalidate any previous LL to the same address.
 253      */
 254     void trackLoadLocked(PacketPtr pkt)
 255     {
 256         assert(pkt->isLLSC());
 257         auto l = lockList.begin();
 258         while (l != lockList.end()) {
 259             if (l->intersects(pkt->req))
 260                 l = lockList.erase(l);
 261             else
 262                 ++l;
 263         }
 264
 265         lockList.emplace_front(pkt->req);
 266     }
 267
 268     /**
 269      * Clear the any load lock that intersect the request, and is from
 270      * a different context.
 271      */
 272     void clearLoadLocks(RequestPtr req)
 273     {
 274         auto l = lockList.begin();
 275         while (l != lockList.end()) {
 276             if (l->intersects(req) && l->contextId != req->contextId()) {
 277                 l = lockList.erase(l);
 278             } else {
 279                 ++l;
 280             }
 281         }
 282     }
 283
 284     /**
 285      * Pretty-print a tag, and interpret state bits to readable form
 286      * including mapping to a MOESI state.
 287      *
 288      * @return string with basic state information
 289      */
 290     std::string print() const
 291     {
 292         /**
 293          *  state       M   O   E   S   I
 294          *  writable    1   0   1   0   0
 295          *  dirty       1   1   0   0   0
 296          *  valid       1   1   1   1   0
 297          *
 298          *  state   writable    dirty   valid
 299          *  M       1           1       1
 300          *  O       0           1       1
 301          *  E       1           0       1
 302          *  S       0           0       1
 303          *  I       0           0       0
 304          *
 305          * Note that only one cache ever has a block in Modified or
 306          * Owned state, i.e., only one cache owns the block, or
 307          * equivalently has the BlkDirty bit set. However, multiple
 308          * caches on the same path to memory can have a block in the
 309          * Exclusive state (despite the name). Exclusive means this
 310          * cache has the only copy at this level of the hierarchy,
 311          * i.e., there may be copies in caches above this cache (in
 312          * various states), but there are no peers that have copies on
 313          * this branch of the hierarchy, and no caches at or above
 314          * this level on any other branch have copies either.
 315          **/
 316         unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
 317         char s = '?';
 318         switch (state) {
 319           case 0b111: s = 'M'; break;
 320           case 0b011: s = 'O'; break;
 321           case 0b101: s = 'E'; break;
 322           case 0b001: s = 'S'; break;
 323           case 0b000: s = 'I'; break;
 324           default:    s = 'T'; break; // @TODO add other types
 325         }
 326         return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
 327                         "dirty: %d tag: %x", status, s, isValid(),
 328                         isWritable(), isReadable(), isDirty(), tag);
 329     }
 330
 331     /**
 332      * Handle interaction of load-locked operations and stores.
 333      * @return True if write should proceed, false otherwise.  Returns
 334      * false only in the case of a failed store conditional.
 335      */
 336     bool checkWrite(PacketPtr pkt)
 337     {
 338         assert(pkt->isWrite());
 339
 340         // common case
 341         if (!pkt->isLLSC() && lockList.empty())
 342             return true;
 343
 344         RequestPtr req = pkt->req;
 345
 346         if (pkt->isLLSC()) {
 347             // it's a store conditional... have to check for matching
 348             // load locked.
 349             bool success = false;
 350
 351             auto l = lockList.begin();
 352             while (!success && l != lockList.end()) {
 353                 if (l->matches(pkt->req)) {
 354                     // it's a store conditional, and as far as the
 355                     // memory system can tell, the requesting
 356                     // context's lock is still valid.
 357                     success = true;
 358                     lockList.erase(l);
 359                 } else {
 360                     ++l;
 361                 }
 362             }
 363
 364             req->setExtraData(success ? 1 : 0);
 365             // clear any intersected locks from other contexts (our LL
 366             // should already have cleared them)
 367             clearLoadLocks(req);
 368             return success;
 369         } else {
 370             // a normal write, if there is any lock not from this
 371             // context we clear the list, thus for a private cache we
 372             // never clear locks on normal writes
 373             clearLoadLocks(req);
 374             return true;
 375         }
 376     }
 377 };
 378
 379 /**
 380  * Simple class to provide virtual print() method on cache blocks
 381  * without allocating a vtable pointer for every single cache block.
 382  * Just wrap the CacheBlk object in an instance of this before passing
 383  * to a function that requires a Printable object.
 384  */
 385 class CacheBlkPrintWrapper : public Printable
 386 {
 387     CacheBlk *blk;
 388   public:
 389     CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
 390     virtual ~CacheBlkPrintWrapper() {}
 391     void print(std::ostream &o, int verbosity = 0,
 392                const std::string &prefix = "") const;
 393 };
 394
 395 /**
 396  * Base class for cache block visitor, operating on the cache block
 397  * base class (later subclassed for the various tag classes). This
 398  * visitor class is used as part of the forEachBlk interface in the
 399  * tag classes.
 400  */
 401 class CacheBlkVisitor
 402 {
 403   public:
 404
 405     CacheBlkVisitor() {}
 406     virtual ~CacheBlkVisitor() {}
 407
 408     virtual bool operator()(CacheBlk &blk) = 0;
 409 };
 410
 411 #endif //__MEM_CACHE_BLK_HH__