2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 * Definitions of a simple cache block class.
35 #ifndef __CACHE_BLK_HH__
36 #define __CACHE_BLK_HH__
40 #include "base/printable.hh"
41 #include "mem/packet.hh"
42 #include "mem/request.hh"
43 #include "sim/core.hh" // for Tick
46 * Cache block status bit assignments
48 enum CacheBlkStatusBits {
49 /** valid, readable */
51 /** write permission */
53 /** read permission (yes, block can be valid but not readable) */
55 /** dirty (modified) */
57 /** block was referenced */
59 /** block was a hardware prefetch yet unaccessed*/
60 BlkHWPrefetched = 0x20
64 * A Basic Cache block.
65 * Contains the tag, status, and a pointer to data.
70 /** The address space ID of this block. */
72 /** Data block tag value. */
75 * Contains a copy of the data in this block for easy access. This is used
76 * for efficient execution when the data could be actually stored in
77 * another format (COW, compressed, sub-blocked, etc). In all cases the
78 * data stored here should be kept consistant with the actual data
79 * referenced by this block.
82 /** the number of bytes stored in this block. */
85 /** block state: OR of CacheBlkStatusBit */
86 typedef unsigned State;
88 /** The current status of this block. @sa CacheBlockStatusBits */
91 /** Which curTick() will this block be accessable */
95 * The set this block belongs to.
96 * @todo Move this into subclasses when we fix CacheTags to use them.
100 /** whether this block has been touched */
103 /** Number of references to this block since it was brought in. */
106 /** holds the source requestor ID for this block. */
111 * Represents that the indicated thread context has a "lock" on
112 * the block, in the LL/SC sense.
116 int contextId; // locking context
118 // check for matching execution context
119 bool matchesContext(Request *req)
121 return (contextId == req->contextId());
125 : contextId(req->contextId())
130 /** List of thread contexts that have performed a load-locked (LL)
131 * on the block since the last store. */
132 std::list<Lock> lockList;
137 : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
138 set(-1), isTouched(false), refCount(0),
139 srcMasterId(Request::invldMasterId)
143 * Copy the state of the given block into this one.
144 * @param rhs The block to copy.
145 * @return a const reference to this block.
147 const CacheBlk& operator=(const CacheBlk& rhs)
154 whenReady = rhs.whenReady;
156 refCount = rhs.refCount;
161 * Checks the write permissions of this block.
162 * @return True if the block is writable.
164 bool isWritable() const
166 const State needed_bits = BlkWritable | BlkValid;
167 return (status & needed_bits) == needed_bits;
171 * Checks the read permissions of this block. Note that a block
172 * can be valid but not readable if there is an outstanding write
174 * @return True if the block is readable.
176 bool isReadable() const
178 const State needed_bits = BlkReadable | BlkValid;
179 return (status & needed_bits) == needed_bits;
183 * Checks that a block is valid.
184 * @return True if the block is valid.
188 return (status & BlkValid) != 0;
192 * Invalidate the block and clear all state.
202 * Check to see if a block has been written.
203 * @return True if the block is dirty.
207 return (status & BlkDirty) != 0;
211 * Check if this block has been referenced.
212 * @return True if the block has been referenced.
214 bool isReferenced() const
216 return (status & BlkReferenced) != 0;
220 * Check if this block was the result of a hardware prefetch, yet to
222 * @return True if the block was a hardware prefetch, unaccesed.
224 bool wasPrefetched() const
226 return (status & BlkHWPrefetched) != 0;
230 * Track the fact that a local locked was issued to the block. If
231 * multiple LLs get issued from the same context we could have
232 * redundant records on the list, but that's OK, as they'll all
233 * get blown away at the next store.
235 void trackLoadLocked(PacketPtr pkt)
237 assert(pkt->isLLSC());
238 lockList.push_front(Lock(pkt->req));
242 * Clear the list of valid load locks. Should be called whenever
243 * block is written to or invalidated.
245 void clearLoadLocks() { lockList.clear(); }
248 * Handle interaction of load-locked operations and stores.
249 * @return True if write should proceed, false otherwise. Returns
250 * false only in the case of a failed store conditional.
252 bool checkWrite(PacketPtr pkt)
254 Request *req = pkt->req;
256 // it's a store conditional... have to check for matching
258 bool success = false;
260 for (std::list<Lock>::iterator i = lockList.begin();
261 i != lockList.end(); ++i)
263 if (i->matchesContext(req)) {
264 // it's a store conditional, and as far as the memory
265 // system can tell, the requesting context's lock is
272 req->setExtraData(success ? 1 : 0);
276 // for *all* stores (conditional or otherwise) we have to
277 // clear the list of load-locks as they're all invalid now.
285 * Simple class to provide virtual print() method on cache blocks
286 * without allocating a vtable pointer for every single cache block.
287 * Just wrap the CacheBlk object in an instance of this before passing
288 * to a function that requires a Printable object.
290 class CacheBlkPrintWrapper : public Printable
294 CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
295 virtual ~CacheBlkPrintWrapper() {}
296 void print(std::ostream &o, int verbosity = 0,
297 const std::string &prefix = "") const;
302 #endif //__CACHE_BLK_HH__