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40 * Authors: Erik Hallnor
45 * Definitions of a simple cache block class.
48 #ifndef __MEM_CACHE_BLK_HH__
49 #define __MEM_CACHE_BLK_HH__
57 #include "base/printable.hh"
58 #include "base/types.hh"
59 #include "mem/cache/replacement_policies/base.hh"
60 #include "mem/packet.hh"
61 #include "mem/request.hh"
64 * Cache block status bit assignments
66 enum CacheBlkStatusBits : unsigned {
67 /** valid, readable */
69 /** write permission */
71 /** read permission (yes, block can be valid but not readable) */
73 /** dirty (modified) */
75 /** block was a hardware prefetch yet unaccessed*/
76 BlkHWPrefetched = 0x20,
77 /** block holds data from the secure memory space */
82 * A Basic Cache block.
83 * Contains the tag, status, and a pointer to data.
85 class CacheBlk : public ReplaceableEntry
88 /** Task Id associated with this block */
91 /** Data block tag value. */
94 * Contains a copy of the data in this block for easy access. This is used
95 * for efficient execution when the data could be actually stored in
96 * another format (COW, compressed, sub-blocked, etc). In all cases the
97 * data stored here should be kept consistant with the actual data
98 * referenced by this block.
102 /** block state: OR of CacheBlkStatusBit */
103 typedef unsigned State;
105 /** The current status of this block. @sa CacheBlockStatusBits */
108 /** Which curTick() will this block be accessible */
111 /** Number of references to this block since it was brought in. */
114 /** holds the source requestor ID for this block. */
117 /** Tick on which the block was inserted in the cache. */
122 * Represents that the indicated thread context has a "lock" on
123 * the block, in the LL/SC sense.
127 ContextID contextId; // locking context
128 Addr lowAddr; // low address of lock range
129 Addr highAddr; // high address of lock range
131 // check for matching execution context, and an address that
132 // is within the lock
133 bool matches(const RequestPtr &req) const
135 Addr req_low = req->getPaddr();
136 Addr req_high = req_low + req->getSize() -1;
137 return (contextId == req->contextId()) &&
138 (req_low >= lowAddr) && (req_high <= highAddr);
141 // check if a request is intersecting and thus invalidating the lock
142 bool intersects(const RequestPtr &req) const
144 Addr req_low = req->getPaddr();
145 Addr req_high = req_low + req->getSize() - 1;
147 return (req_low <= highAddr) && (req_high >= lowAddr);
150 Lock(const RequestPtr &req)
151 : contextId(req->contextId()),
152 lowAddr(req->getPaddr()),
153 highAddr(lowAddr + req->getSize() - 1)
158 /** List of thread contexts that have performed a load-locked (LL)
159 * on the block since the last store. */
160 std::list<Lock> lockList;
163 CacheBlk() : data(nullptr)
168 CacheBlk(const CacheBlk&) = delete;
169 CacheBlk& operator=(const CacheBlk&) = delete;
170 virtual ~CacheBlk() {};
173 * Checks the write permissions of this block.
174 * @return True if the block is writable.
176 bool isWritable() const
178 const State needed_bits = BlkWritable | BlkValid;
179 return (status & needed_bits) == needed_bits;
183 * Checks the read permissions of this block. Note that a block
184 * can be valid but not readable if there is an outstanding write
186 * @return True if the block is readable.
188 bool isReadable() const
190 const State needed_bits = BlkReadable | BlkValid;
191 return (status & needed_bits) == needed_bits;
195 * Checks that a block is valid.
196 * @return True if the block is valid.
200 return (status & BlkValid) != 0;
204 * Invalidate the block and clear all state.
206 virtual void invalidate()
209 task_id = ContextSwitchTaskId::Unknown;
213 srcMasterId = Request::invldMasterId;
214 tickInserted = MaxTick;
219 * Check to see if a block has been written.
220 * @return True if the block is dirty.
224 return (status & BlkDirty) != 0;
228 * Check if this block was the result of a hardware prefetch, yet to
230 * @return True if the block was a hardware prefetch, unaccesed.
232 bool wasPrefetched() const
234 return (status & BlkHWPrefetched) != 0;
238 * Check if this block holds data from the secure memory space.
239 * @return True if the block holds data from the secure memory space.
241 bool isSecure() const
243 return (status & BlkSecure) != 0;
247 * Set member variables when a block insertion occurs. Resets reference
248 * count to 1 (the insertion counts as a reference), and touch block if
249 * it hadn't been touched previously. Sets the insertion tick to the
250 * current tick. Does not make block valid.
252 * @param tag Block address tag.
253 * @param is_secure Whether the block is in secure space or not.
254 * @param src_master_ID The source requestor ID.
255 * @param task_ID The new task ID.
257 virtual void insert(const Addr tag, const bool is_secure,
258 const int src_master_ID, const uint32_t task_ID);
261 * Track the fact that a local locked was issued to the
262 * block. Invalidate any previous LL to the same address.
264 void trackLoadLocked(PacketPtr pkt)
266 assert(pkt->isLLSC());
267 auto l = lockList.begin();
268 while (l != lockList.end()) {
269 if (l->intersects(pkt->req))
270 l = lockList.erase(l);
275 lockList.emplace_front(pkt->req);
279 * Clear the any load lock that intersect the request, and is from
280 * a different context.
282 void clearLoadLocks(const RequestPtr &req)
284 auto l = lockList.begin();
285 while (l != lockList.end()) {
286 if (l->intersects(req) && l->contextId != req->contextId()) {
287 l = lockList.erase(l);
295 * Pretty-print a tag, and interpret state bits to readable form
296 * including mapping to a MOESI state.
298 * @return string with basic state information
300 std::string print() const
308 * state writable dirty valid
315 * Note that only one cache ever has a block in Modified or
316 * Owned state, i.e., only one cache owns the block, or
317 * equivalently has the BlkDirty bit set. However, multiple
318 * caches on the same path to memory can have a block in the
319 * Exclusive state (despite the name). Exclusive means this
320 * cache has the only copy at this level of the hierarchy,
321 * i.e., there may be copies in caches above this cache (in
322 * various states), but there are no peers that have copies on
323 * this branch of the hierarchy, and no caches at or above
324 * this level on any other branch have copies either.
326 unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
329 case 0b111: s = 'M'; break;
330 case 0b011: s = 'O'; break;
331 case 0b101: s = 'E'; break;
332 case 0b001: s = 'S'; break;
333 case 0b000: s = 'I'; break;
334 default: s = 'T'; break; // @TODO add other types
336 return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
337 "dirty: %d tag: %x", status, s, isValid(),
338 isWritable(), isReadable(), isDirty(), tag);
342 * Handle interaction of load-locked operations and stores.
343 * @return True if write should proceed, false otherwise. Returns
344 * false only in the case of a failed store conditional.
346 bool checkWrite(PacketPtr pkt)
348 assert(pkt->isWrite());
351 if (!pkt->isLLSC() && lockList.empty())
354 const RequestPtr &req = pkt->req;
357 // it's a store conditional... have to check for matching
359 bool success = false;
361 auto l = lockList.begin();
362 while (!success && l != lockList.end()) {
363 if (l->matches(pkt->req)) {
364 // it's a store conditional, and as far as the
365 // memory system can tell, the requesting
366 // context's lock is still valid.
374 req->setExtraData(success ? 1 : 0);
375 // clear any intersected locks from other contexts (our LL
376 // should already have cleared them)
380 // a normal write, if there is any lock not from this
381 // context we clear the list, thus for a private cache we
382 // never clear locks on normal writes
390 * Special instance of CacheBlk for use with tempBlk that deals with its
391 * block address regeneration.
394 class TempCacheBlk final : public CacheBlk
398 * Copy of the block's address, used to regenerate tempBlock's address.
404 * Creates a temporary cache block, with its own storage.
405 * @param size The size (in bytes) of this cache block.
407 TempCacheBlk(unsigned size) : CacheBlk()
409 data = new uint8_t[size];
411 TempCacheBlk(const TempCacheBlk&) = delete;
412 TempCacheBlk& operator=(const TempCacheBlk&) = delete;
413 ~TempCacheBlk() { delete [] data; };
416 * Invalidate the block and clear all state.
418 void invalidate() override {
419 CacheBlk::invalidate();
424 void insert(const Addr addr, const bool is_secure,
425 const int src_master_ID=0, const uint32_t task_ID=0) override
439 * Get block's address.
441 * @return addr Address value.
450 * Simple class to provide virtual print() method on cache blocks
451 * without allocating a vtable pointer for every single cache block.
452 * Just wrap the CacheBlk object in an instance of this before passing
453 * to a function that requires a Printable object.
455 class CacheBlkPrintWrapper : public Printable
459 CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
460 virtual ~CacheBlkPrintWrapper() {}
461 void print(std::ostream &o, int verbosity = 0,
462 const std::string &prefix = "") const;
465 #endif //__MEM_CACHE_BLK_HH__