src/mem/cache/builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "enums/Prefetch.hh"
  40 #include "mem/config/cache.hh"
  41 #include "mem/config/prefetch.hh"
  42 #include "mem/cache/base.hh"
  43 #include "mem/cache/cache.hh"
  44 #include "mem/bus.hh"
  45 #include "params/BaseCache.hh"
  46
  47 // Tag Templates
  48 #if defined(USE_CACHE_LRU)
  49 #include "mem/cache/tags/lru.hh"
  50 #endif
  51
  52 #if defined(USE_CACHE_FALRU)
  53 #include "mem/cache/tags/fa_lru.hh"
  54 #endif
  55
  56 #if defined(USE_CACHE_IIC)
  57 #include "mem/cache/tags/iic.hh"
  58 #endif
  59
  60 //Prefetcher Headers
  61 #if defined(USE_GHB)
  62 #include "mem/cache/prefetch/ghb.hh"
  63 #endif
  64 #if defined(USE_TAGGED)
  65 #include "mem/cache/prefetch/tagged.hh"
  66 #endif
  67 #if defined(USE_STRIDED)
  68 #include "mem/cache/prefetch/stride.hh"
  69 #endif
  70
  71
  72 using namespace std;
  73 using namespace TheISA;
  74
  75 #define BUILD_CACHE(TAGS, tags)                                      \
  76     do {                                                                \
  77         BasePrefetcher *pf;                                             \
  78         if (prefetch_policy == Enums::tagged) {                         \
  79             BUILD_TAGGED_PREFETCHER(TAGS);                              \
  80         }                                                               \
  81         else if (prefetch_policy == Enums::stride) {                    \
  82             BUILD_STRIDED_PREFETCHER(TAGS);                             \
  83         }                                                               \
  84         else if (prefetch_policy == Enums::ghb) {                       \
  85             BUILD_GHB_PREFETCHER(TAGS);                                 \
  86         }                                                               \
  87         else {                                                          \
  88             BUILD_NULL_PREFETCHER(TAGS);                                \
  89         }                                                               \
  90         Cache<TAGS> *retval =                                           \
  91             new Cache<TAGS>(this, tags, pf);                            \
  92         return retval;                                                  \
  93     } while (0)
  94
  95 #define BUILD_CACHE_PANIC(x) do {                       \
  96         panic("%s not compiled into M5", x);            \
  97     } while (0)
  98
  99 #if defined(USE_CACHE_FALRU)
 100 #define BUILD_FALRU_CACHE do {                              \
 101         FALRU *tags = new FALRU(block_size, size, latency); \
 102         BUILD_CACHE(FALRU, tags);                           \
 103     } while (0)
 104 #else
 105 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
 106 #endif
 107
 108 #if defined(USE_CACHE_LRU)
 109 #define BUILD_LRU_CACHE do {                                            \
 110         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 111         BUILD_CACHE(LRU, tags);                                         \
 112     } while (0)
 113 #else
 114 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
 115 #endif
 116
 117 #if defined(USE_CACHE_IIC)
 118 #define BUILD_IIC_CACHE do {                            \
 119         IIC *tags = new IIC(iic_params);                \
 120         BUILD_CACHE(IIC, tags);                         \
 121     } while (0)
 122 #else
 123 #define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
 124 #endif
 125
 126 #define BUILD_CACHES do {                               \
 127         if (repl == NULL) {                             \
 128             if (numSets == 1) {                         \
 129                 BUILD_FALRU_CACHE;                      \
 130             } else {                                    \
 131                BUILD_LRU_CACHE;                    \
 132             }                                           \
 133         } else {                                        \
 134             BUILD_IIC_CACHE;                            \
 135         }                                               \
 136     } while (0)
 137
 138 #define BUILD_COHERENCE(b) do {                                         \
 139     } while (0)
 140
 141 #if defined(USE_TAGGED)
 142 #define BUILD_TAGGED_PREFETCHER(t)                                      \
 143     pf = new TaggedPrefetcher(this)
 144 #else
 145 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 146 #endif
 147
 148 #if defined(USE_STRIDED)
 149 #define BUILD_STRIDED_PREFETCHER(t)                                     \
 150     pf = new StridePrefetcher(this)
 151 #else
 152 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 153 #endif
 154
 155 #if defined(USE_GHB)
 156 #define BUILD_GHB_PREFETCHER(t)                                         \
 157     pf = new GHBPrefetcher(this)
 158 #else
 159 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 160 #endif
 161
 162 #if defined(USE_TAGGED)
 163 #define BUILD_NULL_PREFETCHER(t)                                        \
 164     pf = new TaggedPrefetcher(this)
 165 #else
 166 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 167 #endif
 168
 169 BaseCache *
 170 BaseCacheParams::create()
 171 {
 172     int numSets = size / (assoc * block_size);
 173     if (subblock_size == 0) {
 174         subblock_size = block_size;
 175     }
 176
 177     //Warnings about prefetcher policy
 178     if (prefetch_policy == Enums::none) {
 179         if (prefetch_miss || prefetch_access)
 180             panic("With no prefetcher, you shouldn't prefetch from"
 181                   " either miss or access stream\n");
 182     }
 183
 184     if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
 185         prefetch_policy == Enums::ghb) {
 186
 187         if (!prefetch_miss && !prefetch_access)
 188             warn("With this prefetcher you should chose a prefetch"
 189                  " stream (miss or access)\nNo Prefetching will occur\n");
 190
 191         if (prefetch_miss && prefetch_access)
 192             panic("Can't do prefetches from both miss and access stream");
 193     }
 194
 195 #if defined(USE_CACHE_IIC)
 196     // Build IIC params
 197     IIC::Params iic_params;
 198     iic_params.size = size;
 199     iic_params.numSets = numSets;
 200     iic_params.blkSize = block_size;
 201     iic_params.assoc = assoc;
 202     iic_params.hashDelay = hash_delay;
 203     iic_params.hitLatency = latency;
 204     iic_params.rp = repl;
 205     iic_params.subblockSize = subblock_size;
 206 #else
 207     const void *repl = NULL;
 208 #endif
 209
 210     BUILD_CACHES;
 211     return NULL;
 212 }