2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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28 * Authors: Erik Hallnor
34 * Simobject instatiation of caches.
39 #include "config/the_isa.hh"
40 #include "mem/cache/base.hh"
41 #include "mem/cache/cache.hh"
42 #include "mem/config/cache.hh"
43 #include "params/BaseCache.hh"
46 #if defined(USE_CACHE_LRU)
47 #include "mem/cache/tags/lru.hh"
50 #if defined(USE_CACHE_FALRU)
51 #include "mem/cache/tags/fa_lru.hh"
57 #define BUILD_CACHE(TAGS, tags) \
59 Cache<TAGS> *retval = \
60 new Cache<TAGS>(this, tags); \
64 #define BUILD_CACHE_PANIC(x) do { \
65 panic("%s not compiled into M5", x); \
68 #if defined(USE_CACHE_FALRU)
69 #define BUILD_FALRU_CACHE do { \
70 FALRU *tags = new FALRU(block_size, size, hit_latency); \
71 BUILD_CACHE(FALRU, tags); \
74 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
77 #if defined(USE_CACHE_LRU)
78 #define BUILD_LRU_CACHE do { \
79 LRU *tags = new LRU(numSets, block_size, assoc, hit_latency); \
80 BUILD_CACHE(LRU, tags); \
83 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
87 BaseCacheParams::create()
89 int numSets
= size
/ (assoc
* block_size
);