src/mem/cache/builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <list>
  37 #include <vector>
  38
  39 #include "config/the_isa.hh"
  40 #include "enums/Prefetch.hh"
  41 #include "mem/cache/base.hh"
  42 #include "mem/cache/cache.hh"
  43 #include "mem/config/cache.hh"
  44 #include "mem/bus.hh"
  45 #include "params/BaseCache.hh"
  46
  47 // Tag Templates
  48 #if defined(USE_CACHE_LRU)
  49 #include "mem/cache/tags/lru.hh"
  50 #endif
  51
  52 #if defined(USE_CACHE_FALRU)
  53 #include "mem/cache/tags/fa_lru.hh"
  54 #endif
  55
  56 #if defined(USE_CACHE_IIC)
  57 #include "mem/cache/tags/iic.hh"
  58 #endif
  59
  60 //Prefetcher Headers
  61 #include "mem/cache/prefetch/ghb.hh"
  62 #include "mem/cache/prefetch/stride.hh"
  63 #include "mem/cache/prefetch/tagged.hh"
  64
  65 using namespace std;
  66
  67 #define BUILD_CACHE(TAGS, tags)                         \
  68     do {                                                \
  69         BasePrefetcher *pf;                             \
  70         if (prefetch_policy == Enums::tagged) {         \
  71             pf = new TaggedPrefetcher(this);            \
  72         }                                               \
  73         else if (prefetch_policy == Enums::stride) {    \
  74             pf = new StridePrefetcher(this);            \
  75         }                                               \
  76         else if (prefetch_policy == Enums::ghb) {       \
  77             pf = new GHBPrefetcher(this);               \
  78         }                                               \
  79         else {                                          \
  80             pf = NULL;                                  \
  81         }                                               \
  82         Cache<TAGS> *retval =                           \
  83             new Cache<TAGS>(this, tags, pf);            \
  84         return retval;                                  \
  85     } while (0)
  86
  87 #define BUILD_CACHE_PANIC(x) do {                       \
  88         panic("%s not compiled into M5", x);            \
  89     } while (0)
  90
  91 #if defined(USE_CACHE_FALRU)
  92 #define BUILD_FALRU_CACHE do {                              \
  93         FALRU *tags = new FALRU(block_size, size, latency); \
  94         BUILD_CACHE(FALRU, tags);                           \
  95     } while (0)
  96 #else
  97 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
  98 #endif
  99
 100 #if defined(USE_CACHE_LRU)
 101 #define BUILD_LRU_CACHE do {                                            \
 102         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 103         BUILD_CACHE(LRU, tags);                                         \
 104     } while (0)
 105 #else
 106 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
 107 #endif
 108
 109 #if defined(USE_CACHE_IIC)
 110 #define BUILD_IIC_CACHE do {                            \
 111         IIC *tags = new IIC(iic_params);                \
 112         BUILD_CACHE(IIC, tags);                         \
 113     } while (0)
 114 #else
 115 #define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
 116 #endif
 117
 118 #define BUILD_CACHES do {                               \
 119         if (repl == NULL) {                             \
 120             if (numSets == 1) {                         \
 121                 BUILD_FALRU_CACHE;                      \
 122             } else {                                    \
 123                BUILD_LRU_CACHE;                    \
 124             }                                           \
 125         } else {                                        \
 126             BUILD_IIC_CACHE;                            \
 127         }                                               \
 128     } while (0)
 129
 130 BaseCache *
 131 BaseCacheParams::create()
 132 {
 133     int numSets = size / (assoc * block_size);
 134     if (subblock_size == 0) {
 135         subblock_size = block_size;
 136     }
 137
 138 #if defined(USE_CACHE_IIC)
 139     // Build IIC params
 140     IIC::Params iic_params;
 141     iic_params.size = size;
 142     iic_params.numSets = numSets;
 143     iic_params.blkSize = block_size;
 144     iic_params.assoc = assoc;
 145     iic_params.hashDelay = hash_delay;
 146     iic_params.hitLatency = latency;
 147     iic_params.rp = repl;
 148     iic_params.subblockSize = subblock_size;
 149 #else
 150     const void *repl = NULL;
 151 #endif
 152
 153     BUILD_CACHES;
 154     return NULL;
 155 }