src/mem/cache/builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <list>
  37 #include <vector>
  38
  39 #include "config/the_isa.hh"
  40 #include "mem/cache/base.hh"
  41 #include "mem/cache/cache.hh"
  42 #include "mem/config/cache.hh"
  43 #include "mem/bus.hh"
  44 #include "params/BaseCache.hh"
  45
  46 // Tag Templates
  47 #if defined(USE_CACHE_LRU)
  48 #include "mem/cache/tags/lru.hh"
  49 #endif
  50
  51 #if defined(USE_CACHE_FALRU)
  52 #include "mem/cache/tags/fa_lru.hh"
  53 #endif
  54
  55 #if defined(USE_CACHE_IIC)
  56 #include "mem/cache/tags/iic.hh"
  57 #endif
  58
  59
  60 using namespace std;
  61
  62 #define BUILD_CACHE(TAGS, tags)                         \
  63     do {                                                \
  64         Cache<TAGS> *retval =                           \
  65             new Cache<TAGS>(this, tags);            \
  66         return retval;                                  \
  67     } while (0)
  68
  69 #define BUILD_CACHE_PANIC(x) do {                       \
  70         panic("%s not compiled into M5", x);            \
  71     } while (0)
  72
  73 #if defined(USE_CACHE_FALRU)
  74 #define BUILD_FALRU_CACHE do {                              \
  75         FALRU *tags = new FALRU(block_size, size, latency); \
  76         BUILD_CACHE(FALRU, tags);                           \
  77     } while (0)
  78 #else
  79 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
  80 #endif
  81
  82 #if defined(USE_CACHE_LRU)
  83 #define BUILD_LRU_CACHE do {                                            \
  84         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
  85         BUILD_CACHE(LRU, tags);                                         \
  86     } while (0)
  87 #else
  88 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
  89 #endif
  90
  91 #if defined(USE_CACHE_IIC)
  92 #define BUILD_IIC_CACHE do {                            \
  93         IIC *tags = new IIC(iic_params);                \
  94         BUILD_CACHE(IIC, tags);                         \
  95     } while (0)
  96 #else
  97 #define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
  98 #endif
  99
 100 #define BUILD_CACHES do {                               \
 101         if (repl == NULL) {                             \
 102             if (numSets == 1) {                         \
 103                 BUILD_FALRU_CACHE;                      \
 104             } else {                                    \
 105                BUILD_LRU_CACHE;                    \
 106             }                                           \
 107         } else {                                        \
 108             BUILD_IIC_CACHE;                            \
 109         }                                               \
 110     } while (0)
 111
 112 BaseCache *
 113 BaseCacheParams::create()
 114 {
 115     int numSets = size / (assoc * block_size);
 116     if (subblock_size == 0) {
 117         subblock_size = block_size;
 118     }
 119
 120 #if defined(USE_CACHE_IIC)
 121     // Build IIC params
 122     IIC::Params iic_params;
 123     iic_params.size = size;
 124     iic_params.numSets = numSets;
 125     iic_params.blkSize = block_size;
 126     iic_params.assoc = assoc;
 127     iic_params.hashDelay = hash_delay;
 128     iic_params.hitLatency = latency;
 129     iic_params.rp = repl;
 130     iic_params.subblockSize = subblock_size;
 131 #else
 132     const void *repl = NULL;
 133 #endif
 134
 135     BUILD_CACHES;
 136     return NULL;
 137 }