2 * Copyright (c) 2010-2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Erik Hallnor
54 #include "mem/cache/cache.hh"
56 #include "base/misc.hh"
57 #include "base/types.hh"
58 #include "debug/Cache.hh"
59 #include "debug/CachePort.hh"
60 #include "debug/CacheTags.hh"
61 #include "mem/cache/blk.hh"
62 #include "mem/cache/mshr.hh"
63 #include "mem/cache/prefetch/base.hh"
64 #include "sim/sim_exit.hh"
66 Cache::Cache(const CacheParams
*p
)
67 : BaseCache(p
, p
->system
->cacheLineSize()),
69 prefetcher(p
->prefetcher
),
71 prefetchOnAccess(p
->prefetch_on_access
)
73 tempBlock
= new CacheBlk();
74 tempBlock
->data
= new uint8_t[blkSize
];
76 cpuSidePort
= new CpuSidePort(p
->name
+ ".cpu_side", this,
78 memSidePort
= new MemSidePort(p
->name
+ ".mem_side", this,
83 prefetcher
->setCache(this);
88 delete [] tempBlock
->data
;
98 BaseCache::regStats();
102 Cache::cmpAndSwap(CacheBlk
*blk
, PacketPtr pkt
)
104 assert(pkt
->isRequest());
106 uint64_t overwrite_val
;
108 uint64_t condition_val64
;
109 uint32_t condition_val32
;
111 int offset
= tags
->extractBlkOffset(pkt
->getAddr());
112 uint8_t *blk_data
= blk
->data
+ offset
;
114 assert(sizeof(uint64_t) >= pkt
->getSize());
116 overwrite_mem
= true;
117 // keep a copy of our possible write value, and copy what is at the
118 // memory address into the packet
119 pkt
->writeData((uint8_t *)&overwrite_val
);
120 pkt
->setData(blk_data
);
122 if (pkt
->req
->isCondSwap()) {
123 if (pkt
->getSize() == sizeof(uint64_t)) {
124 condition_val64
= pkt
->req
->getExtraData();
125 overwrite_mem
= !std::memcmp(&condition_val64
, blk_data
,
127 } else if (pkt
->getSize() == sizeof(uint32_t)) {
128 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
129 overwrite_mem
= !std::memcmp(&condition_val32
, blk_data
,
132 panic("Invalid size for conditional read/write\n");
136 std::memcpy(blk_data
, &overwrite_val
, pkt
->getSize());
137 blk
->status
|= BlkDirty
;
143 Cache::satisfyCpuSideRequest(PacketPtr pkt
, CacheBlk
*blk
,
144 bool deferred_response
, bool pending_downgrade
)
146 assert(pkt
->isRequest());
148 assert(blk
&& blk
->isValid());
149 // Occasionally this is not true... if we are a lower-level cache
150 // satisfying a string of Read and ReadEx requests from
151 // upper-level caches, a Read will mark the block as shared but we
152 // can satisfy a following ReadEx anyway since we can rely on the
153 // Read requester(s) to have buffered the ReadEx snoop and to
154 // invalidate their blocks after receiving them.
155 // assert(!pkt->needsExclusive() || blk->isWritable());
156 assert(pkt
->getOffset(blkSize
) + pkt
->getSize() <= blkSize
);
158 // Check RMW operations first since both isRead() and
159 // isWrite() will be true for them
160 if (pkt
->cmd
== MemCmd::SwapReq
) {
161 cmpAndSwap(blk
, pkt
);
162 } else if (pkt
->isWrite()) {
163 assert(blk
->isWritable());
164 // Write or WriteLine at the first cache with block in Exclusive
165 if (blk
->checkWrite(pkt
)) {
166 pkt
->writeDataToBlock(blk
->data
, blkSize
);
168 // Always mark the line as dirty even if we are a failed
169 // StoreCond so we supply data to any snoops that have
170 // appended themselves to this cache before knowing the store
172 blk
->status
|= BlkDirty
;
173 DPRINTF(Cache
, "%s for %s addr %#llx size %d (write)\n", __func__
,
174 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
175 } else if (pkt
->isRead()) {
177 blk
->trackLoadLocked(pkt
);
179 pkt
->setDataFromBlock(blk
->data
, blkSize
);
180 // determine if this read is from a (coherent) cache, or not
181 // by looking at the command type; we could potentially add a
182 // packet attribute such as 'FromCache' to make this check a
184 if (pkt
->cmd
== MemCmd::ReadExReq
||
185 pkt
->cmd
== MemCmd::ReadSharedReq
||
186 pkt
->cmd
== MemCmd::ReadCleanReq
||
187 pkt
->cmd
== MemCmd::SCUpgradeFailReq
) {
188 assert(pkt
->getSize() == blkSize
);
189 // special handling for coherent block requests from
190 // upper-level caches
191 if (pkt
->needsExclusive()) {
193 assert(pkt
->cmd
== MemCmd::ReadExReq
||
194 pkt
->cmd
== MemCmd::SCUpgradeFailReq
);
196 // if we have a dirty copy, make sure the recipient
197 // keeps it marked dirty
198 if (blk
->isDirty()) {
199 pkt
->assertMemInhibit();
201 // on ReadExReq we give up our copy unconditionally
202 if (blk
!= tempBlock
)
203 tags
->invalidate(blk
);
205 } else if (blk
->isWritable() && !pending_downgrade
&&
206 !pkt
->sharedAsserted() &&
207 pkt
->cmd
!= MemCmd::ReadCleanReq
) {
208 // we can give the requester an exclusive copy (by not
209 // asserting shared line) on a read request if:
210 // - we have an exclusive copy at this level (& below)
211 // - we don't have a pending snoop from below
212 // signaling another read request
213 // - no other cache above has a copy (otherwise it
214 // would have asseretd shared line on request)
215 // - we are not satisfying an instruction fetch (this
216 // prevents dirty data in the i-cache)
218 if (blk
->isDirty()) {
219 // special considerations if we're owner:
220 if (!deferred_response
) {
221 // if we are responding immediately and can
222 // signal that we're transferring ownership
223 // along with exclusivity, do so
224 pkt
->assertMemInhibit();
225 blk
->status
&= ~BlkDirty
;
227 // if we're responding after our own miss,
228 // there's a window where the recipient didn't
229 // know it was getting ownership and may not
230 // have responded to snoops correctly, so we
231 // can't pass off ownership *or* exclusivity
236 // otherwise only respond with a shared copy
241 // Upgrade or Invalidate, since we have it Exclusively (E or
242 // M), we ack then invalidate.
243 assert(pkt
->isUpgrade() || pkt
->isInvalidate());
244 assert(blk
!= tempBlock
);
245 tags
->invalidate(blk
);
247 DPRINTF(Cache
, "%s for %s addr %#llx size %d (invalidation)\n",
248 __func__
, pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
253 /////////////////////////////////////////////////////
255 // MSHR helper functions
257 /////////////////////////////////////////////////////
261 Cache::markInService(MSHR
*mshr
, bool pending_dirty_resp
)
263 markInServiceInternal(mshr
, pending_dirty_resp
);
268 Cache::squash(int threadNum
)
270 bool unblock
= false;
271 BlockedCause cause
= NUM_BLOCKED_CAUSES
;
273 if (noTargetMSHR
&& noTargetMSHR
->threadNum
== threadNum
) {
276 cause
= Blocked_NoTargets
;
278 if (mshrQueue
.isFull()) {
280 cause
= Blocked_NoMSHRs
;
282 mshrQueue
.squash(threadNum
);
283 if (unblock
&& !mshrQueue
.isFull()) {
288 /////////////////////////////////////////////////////
290 // Access path: requests coming in from the CPU side
292 /////////////////////////////////////////////////////
295 Cache::access(PacketPtr pkt
, CacheBlk
*&blk
, Cycles
&lat
,
296 PacketList
&writebacks
)
299 assert(pkt
->isRequest());
301 chatty_assert(!(isReadOnly
&& pkt
->isWrite()),
302 "Should never see a write in a read-only cache %s\n",
305 DPRINTF(Cache
, "%s for %s addr %#llx size %d\n", __func__
,
306 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
308 if (pkt
->req
->isUncacheable()) {
309 DPRINTF(Cache
, "%s%s addr %#llx uncacheable\n", pkt
->cmdString(),
310 pkt
->req
->isInstFetch() ? " (ifetch)" : "",
313 if (pkt
->req
->isClearLL())
316 // flush and invalidate any existing block
317 CacheBlk
*old_blk(tags
->findBlock(pkt
->getAddr(), pkt
->isSecure()));
318 if (old_blk
&& old_blk
->isValid()) {
319 if (old_blk
->isDirty())
320 writebacks
.push_back(writebackBlk(old_blk
));
322 writebacks
.push_back(cleanEvictBlk(old_blk
));
323 tags
->invalidate(old_blk
);
324 old_blk
->invalidate();
328 // lookupLatency is the latency in case the request is uncacheable.
333 ContextID id
= pkt
->req
->hasContextId() ?
334 pkt
->req
->contextId() : InvalidContextID
;
335 // Here lat is the value passed as parameter to accessBlock() function
336 // that can modify its value.
337 blk
= tags
->accessBlock(pkt
->getAddr(), pkt
->isSecure(), lat
, id
);
339 DPRINTF(Cache
, "%s%s addr %#llx size %d (%s) %s\n", pkt
->cmdString(),
340 pkt
->req
->isInstFetch() ? " (ifetch)" : "",
341 pkt
->getAddr(), pkt
->getSize(), pkt
->isSecure() ? "s" : "ns",
342 blk
? "hit " + blk
->print() : "miss");
345 if (pkt
->evictingBlock()) {
346 // We check for presence of block in above caches before issuing
347 // Writeback or CleanEvict to write buffer. Therefore the only
348 // possible cases can be of a CleanEvict packet coming from above
349 // encountering a Writeback generated in this cache peer cache and
350 // waiting in the write buffer. Cases of upper level peer caches
351 // generating CleanEvict and Writeback or simply CleanEvict and
352 // CleanEvict almost simultaneously will be caught by snoops sent out
354 std::vector
<MSHR
*> outgoing
;
355 if (writeBuffer
.findMatches(pkt
->getAddr(), pkt
->isSecure(),
357 assert(outgoing
.size() == 1);
358 PacketPtr wbPkt
= outgoing
[0]->getTarget()->pkt
;
359 assert(pkt
->cmd
== MemCmd::CleanEvict
&&
360 wbPkt
->cmd
== MemCmd::Writeback
);
361 // As the CleanEvict is coming from above, it would have snooped
362 // into other peer caches of the same level while traversing the
363 // crossbar. If a copy of the block had been found, the CleanEvict
364 // would have been deleted in the crossbar. Now that the
365 // CleanEvict is here we can be sure none of the other upper level
366 // caches connected to this cache have the block, so we can clear
367 // the BLOCK_CACHED flag in the Writeback if set and discard the
368 // CleanEvict by returning true.
369 wbPkt
->clearBlockCached();
374 // Writeback handling is special case. We can write the block into
375 // the cache without having a writeable copy (or any copy at all).
376 if (pkt
->cmd
== MemCmd::Writeback
) {
377 assert(blkSize
== pkt
->getSize());
379 // need to do a replacement
380 blk
= allocateBlock(pkt
->getAddr(), pkt
->isSecure(), writebacks
);
382 // no replaceable block available: give up, fwd to next level.
386 tags
->insertBlock(pkt
, blk
);
388 blk
->status
= (BlkValid
| BlkReadable
);
389 if (pkt
->isSecure()) {
390 blk
->status
|= BlkSecure
;
393 blk
->status
|= BlkDirty
;
394 // if shared is not asserted we got the writeback in modified
395 // state, if it is asserted we are in the owned state
396 if (!pkt
->sharedAsserted()) {
397 blk
->status
|= BlkWritable
;
399 // nothing else to do; writeback doesn't expect response
400 assert(!pkt
->needsResponse());
401 std::memcpy(blk
->data
, pkt
->getConstPtr
<uint8_t>(), blkSize
);
402 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
405 } else if (pkt
->cmd
== MemCmd::CleanEvict
) {
407 // Found the block in the tags, need to stop CleanEvict from
408 // propagating further down the hierarchy. Returning true will
409 // treat the CleanEvict like a satisfied write request and delete
413 // We didn't find the block here, propagate the CleanEvict further
414 // down the memory hierarchy. Returning false will treat the CleanEvict
415 // like a Writeback which could not find a replaceable block so has to
418 } else if ((blk
!= NULL
) &&
419 (pkt
->needsExclusive() ? blk
->isWritable()
420 : blk
->isReadable())) {
421 // OK to satisfy access
423 satisfyCpuSideRequest(pkt
, blk
);
427 // Can't satisfy access normally... either no block (blk == NULL)
428 // or have block but need exclusive & only have shared.
432 if (blk
== NULL
&& pkt
->isLLSC() && pkt
->isWrite()) {
433 // complete miss on store conditional... just give up now
434 pkt
->req
->setExtraData(0);
442 class ForwardResponseRecord
: public Packet::SenderState
446 ForwardResponseRecord() {}
450 Cache::doWritebacks(PacketList
& writebacks
, Tick forward_time
)
452 while (!writebacks
.empty()) {
453 PacketPtr wbPkt
= writebacks
.front();
454 // We use forwardLatency here because we are copying writebacks to
455 // write buffer. Call isCachedAbove for both Writebacks and
456 // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag
457 // in Writebacks and discard CleanEvicts.
458 if (isCachedAbove(wbPkt
)) {
459 if (wbPkt
->cmd
== MemCmd::CleanEvict
) {
460 // Delete CleanEvict because cached copies exist above. The
461 // packet destructor will delete the request object because
462 // this is a non-snoop request packet which does not require a
466 // Set BLOCK_CACHED flag in Writeback and send below, so that
467 // the Writeback does not reset the bit corresponding to this
468 // address in the snoop filter below.
469 wbPkt
->setBlockCached();
470 allocateWriteBuffer(wbPkt
, forward_time
);
473 // If the block is not cached above, send packet below. Both
474 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
475 // reset the bit corresponding to this address in the snoop filter
477 allocateWriteBuffer(wbPkt
, forward_time
);
479 writebacks
.pop_front();
485 Cache::recvTimingSnoopResp(PacketPtr pkt
)
487 DPRINTF(Cache
, "%s for %s addr %#llx size %d\n", __func__
,
488 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
490 assert(pkt
->isResponse());
492 // must be cache-to-cache response from upper to lower level
493 ForwardResponseRecord
*rec
=
494 dynamic_cast<ForwardResponseRecord
*>(pkt
->senderState
);
495 assert(!system
->bypassCaches());
498 // @todo What guarantee do we have that this HardPFResp is
499 // actually for this cache, and not a cache closer to the
501 assert(pkt
->cmd
== MemCmd::HardPFResp
);
502 // Check if it's a prefetch response and handle it. We shouldn't
503 // get any other kinds of responses without FRRs.
504 DPRINTF(Cache
, "Got prefetch response from above for addr %#llx (%s)\n",
505 pkt
->getAddr(), pkt
->isSecure() ? "s" : "ns");
510 pkt
->popSenderState();
512 // forwardLatency is set here because there is a response from an
513 // upper level cache.
514 // To pay the delay that occurs if the packet comes from the bus,
515 // we charge also headerDelay.
516 Tick snoop_resp_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
517 // Reset the timing of the packet.
518 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
519 memSidePort
->schedTimingSnoopResp(pkt
, snoop_resp_time
);
523 Cache::promoteWholeLineWrites(PacketPtr pkt
)
525 // Cache line clearing instructions
526 if (doFastWrites
&& (pkt
->cmd
== MemCmd::WriteReq
) &&
527 (pkt
->getSize() == blkSize
) && (pkt
->getOffset(blkSize
) == 0)) {
528 pkt
->cmd
= MemCmd::WriteLineReq
;
529 DPRINTF(Cache
, "packet promoted from Write to WriteLineReq\n");
534 Cache::recvTimingReq(PacketPtr pkt
)
536 DPRINTF(CacheTags
, "%s tags: %s\n", __func__
, tags
->print());
537 //@todo Add back in MemDebug Calls
538 // MemDebug::cacheAccess(pkt);
541 /// @todo temporary hack to deal with memory corruption issue until
542 /// 4-phase transactions are complete
543 for (int x
= 0; x
< pendingDelete
.size(); x
++)
544 delete pendingDelete
[x
];
545 pendingDelete
.clear();
547 assert(pkt
->isRequest());
549 // Just forward the packet if caches are disabled.
550 if (system
->bypassCaches()) {
551 // @todo This should really enqueue the packet rather
552 bool M5_VAR_USED success
= memSidePort
->sendTimingReq(pkt
);
557 promoteWholeLineWrites(pkt
);
559 if (pkt
->memInhibitAsserted()) {
560 // a cache above us (but not where the packet came from) is
561 // responding to the request
562 DPRINTF(Cache
, "mem inhibited on addr %#llx (%s): not responding\n",
563 pkt
->getAddr(), pkt
->isSecure() ? "s" : "ns");
565 // if the packet needs exclusive, and the cache that has
566 // promised to respond (setting the inhibit flag) is not
567 // providing exclusive (it is in O vs M state), we know that
568 // there may be other shared copies in the system; go out and
569 // invalidate them all
570 if (pkt
->needsExclusive() && !pkt
->isSupplyExclusive()) {
571 // create a downstream express snoop with cleared packet
572 // flags, there is no need to allocate any data as the
573 // packet is merely used to co-ordinate state transitions
574 Packet
*snoop_pkt
= new Packet(pkt
, true, false);
576 // also reset the bus time that the original packet has
578 snoop_pkt
->headerDelay
= snoop_pkt
->payloadDelay
= 0;
580 // make this an instantaneous express snoop, and let the
581 // other caches in the system know that the packet is
582 // inhibited, because we have found the authorative copy
583 // (O) that will supply the right data
584 snoop_pkt
->setExpressSnoop();
585 snoop_pkt
->assertMemInhibit();
587 // this express snoop travels towards the memory, and at
588 // every crossbar it is snooped upwards thus reaching
589 // every cache in the system
590 bool M5_VAR_USED success
= memSidePort
->sendTimingReq(snoop_pkt
);
591 // express snoops always succeed
594 // main memory will delete the packet
597 /// @todo nominally we should just delete the packet here,
598 /// however, until 4-phase stuff we can't because sending
599 /// cache is still relying on it.
600 pendingDelete
.push_back(pkt
);
602 // no need to take any action in this particular cache as the
603 // caches along the path to memory are allowed to keep lines
604 // in a shared state, and a cache above us already committed
609 // anything that is merely forwarded pays for the forward latency and
610 // the delay provided by the crossbar
611 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
613 // We use lookupLatency here because it is used to specify the latency
615 Cycles lat
= lookupLatency
;
616 CacheBlk
*blk
= NULL
;
617 bool satisfied
= false;
619 PacketList writebacks
;
620 // Note that lat is passed by reference here. The function
621 // access() calls accessBlock() which can modify lat value.
622 satisfied
= access(pkt
, blk
, lat
, writebacks
);
624 // copy writebacks to write buffer here to ensure they logically
625 // proceed anything happening below
626 doWritebacks(writebacks
, forward_time
);
629 // Here we charge the headerDelay that takes into account the latencies
630 // of the bus, if the packet comes from it.
631 // The latency charged it is just lat that is the value of lookupLatency
632 // modified by access() function, or if not just lookupLatency.
633 // In case of a hit we are neglecting response latency.
634 // In case of a miss we are neglecting forward latency.
635 Tick request_time
= clockEdge(lat
) + pkt
->headerDelay
;
636 // Here we reset the timing of the packet.
637 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
639 // track time of availability of next prefetch, if any
640 Tick next_pf_time
= MaxTick
;
642 bool needsResponse
= pkt
->needsResponse();
645 // should never be satisfying an uncacheable access as we
646 // flush and invalidate any existing block as part of the
648 assert(!pkt
->req
->isUncacheable());
650 // hit (for all other request types)
652 if (prefetcher
&& (prefetchOnAccess
|| (blk
&& blk
->wasPrefetched()))) {
654 blk
->status
&= ~BlkHWPrefetched
;
656 // Don't notify on SWPrefetch
657 if (!pkt
->cmd
.isSWPrefetch())
658 next_pf_time
= prefetcher
->notify(pkt
);
662 pkt
->makeTimingResponse();
663 // @todo: Make someone pay for this
664 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
666 // In this case we are considering request_time that takes
667 // into account the delay of the xbar, if any, and just
668 // lat, neglecting responseLatency, modelling hit latency
669 // just as lookupLatency or or the value of lat overriden
670 // by access(), that calls accessBlock() function.
671 cpuSidePort
->schedTimingResp(pkt
, request_time
);
673 /// @todo nominally we should just delete the packet here,
674 /// however, until 4-phase stuff we can't because sending cache is
675 /// still relying on it. If the block is found in access(),
676 /// CleanEvict and Writeback messages will be deleted here as
678 pendingDelete
.push_back(pkt
);
683 Addr blk_addr
= blockAlign(pkt
->getAddr());
685 // ignore any existing MSHR if we are dealing with an
686 // uncacheable request
687 MSHR
*mshr
= pkt
->req
->isUncacheable() ? nullptr :
688 mshrQueue
.findMatch(blk_addr
, pkt
->isSecure());
690 // Software prefetch handling:
691 // To keep the core from waiting on data it won't look at
692 // anyway, send back a response with dummy data. Miss handling
693 // will continue asynchronously. Unfortunately, the core will
694 // insist upon freeing original Packet/Request, so we have to
695 // create a new pair with a different lifecycle. Note that this
696 // processing happens before any MSHR munging on the behalf of
697 // this request because this new Request will be the one stored
698 // into the MSHRs, not the original.
699 if (pkt
->cmd
.isSWPrefetch()) {
700 assert(needsResponse
);
701 assert(pkt
->req
->hasPaddr());
702 assert(!pkt
->req
->isUncacheable());
704 // There's no reason to add a prefetch as an additional target
705 // to an existing MSHR. If an outstanding request is already
706 // in progress, there is nothing for the prefetch to do.
707 // If this is the case, we don't even create a request at all.
708 PacketPtr pf
= nullptr;
711 // copy the request and create a new SoftPFReq packet
712 RequestPtr req
= new Request(pkt
->req
->getPaddr(),
714 pkt
->req
->getFlags(),
715 pkt
->req
->masterId());
716 pf
= new Packet(req
, pkt
->cmd
);
718 assert(pf
->getAddr() == pkt
->getAddr());
719 assert(pf
->getSize() == pkt
->getSize());
722 pkt
->makeTimingResponse();
723 // for debugging, set all the bits in the response data
724 // (also keeps valgrind from complaining when debugging settings
725 // print out instruction results)
726 std::memset(pkt
->getPtr
<uint8_t>(), 0xFF, pkt
->getSize());
727 // request_time is used here, taking into account lat and the delay
728 // charged if the packet comes from the xbar.
729 cpuSidePort
->schedTimingResp(pkt
, request_time
);
731 // If an outstanding request is in progress (we found an
732 // MSHR) this is set to null
738 /// @note writebacks will be checked in getNextMSHR()
739 /// for any conflicting requests to the same block
741 //@todo remove hw_pf here
743 // Coalesce unless it was a software prefetch (see above).
745 assert(pkt
->cmd
!= MemCmd::Writeback
);
746 // CleanEvicts corresponding to blocks which have outstanding
747 // requests in MSHRs can be deleted here.
748 if (pkt
->cmd
== MemCmd::CleanEvict
) {
749 pendingDelete
.push_back(pkt
);
751 DPRINTF(Cache
, "%s coalescing MSHR for %s addr %#llx size %d\n",
752 __func__
, pkt
->cmdString(), pkt
->getAddr(),
755 assert(pkt
->req
->masterId() < system
->maxMasters());
756 mshr_hits
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
757 if (mshr
->threadNum
!= 0/*pkt->req->threadId()*/) {
758 mshr
->threadNum
= -1;
760 // We use forward_time here because it is the same
761 // considering new targets. We have multiple
762 // requests for the same address here. It
763 // specifies the latency to allocate an internal
764 // buffer and to schedule an event to the queued
765 // port and also takes into account the additional
766 // delay of the xbar.
767 mshr
->allocateTarget(pkt
, forward_time
, order
++);
768 if (mshr
->getNumTargets() == numTarget
) {
770 setBlocked(Blocked_NoTargets
);
771 // need to be careful with this... if this mshr isn't
772 // ready yet (i.e. time > curTick()), we don't want to
773 // move it ahead of mshrs that are ready
774 // mshrQueue.moveToFront(mshr);
777 // We should call the prefetcher reguardless if the request is
778 // satisfied or not, reguardless if the request is in the MSHR or
779 // not. The request could be a ReadReq hit, but still not
780 // satisfied (potentially because of a prior write to the same
781 // cache line. So, even when not satisfied, tehre is an MSHR
782 // already allocated for this, we need to let the prefetcher know
785 // Don't notify on SWPrefetch
786 if (!pkt
->cmd
.isSWPrefetch())
787 next_pf_time
= prefetcher
->notify(pkt
);
792 assert(pkt
->req
->masterId() < system
->maxMasters());
793 if (pkt
->req
->isUncacheable()) {
794 mshr_uncacheable
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
796 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
799 if (pkt
->evictingBlock() ||
800 (pkt
->req
->isUncacheable() && pkt
->isWrite())) {
801 // We use forward_time here because there is an
802 // uncached memory write, forwarded to WriteBuffer.
803 allocateWriteBuffer(pkt
, forward_time
);
805 if (blk
&& blk
->isValid()) {
806 // should have flushed and have no valid block
807 assert(!pkt
->req
->isUncacheable());
809 // If we have a write miss to a valid block, we
810 // need to mark the block non-readable. Otherwise
811 // if we allow reads while there's an outstanding
812 // write miss, the read could return stale data
813 // out of the cache block... a more aggressive
814 // system could detect the overlap (if any) and
815 // forward data out of the MSHRs, but we don't do
816 // that yet. Note that we do need to leave the
817 // block valid so that it stays in the cache, in
818 // case we get an upgrade response (and hence no
819 // new data) when the write miss completes.
820 // As long as CPUs do proper store/load forwarding
821 // internally, and have a sufficiently weak memory
822 // model, this is probably unnecessary, but at some
823 // point it must have seemed like we needed it...
824 assert(pkt
->needsExclusive());
825 assert(!blk
->isWritable());
826 blk
->status
&= ~BlkReadable
;
828 // Here we are using forward_time, modelling the latency of
829 // a miss (outbound) just as forwardLatency, neglecting the
830 // lookupLatency component.
831 allocateMissBuffer(pkt
, forward_time
);
835 // Don't notify on SWPrefetch
836 if (!pkt
->cmd
.isSWPrefetch())
837 next_pf_time
= prefetcher
->notify(pkt
);
842 if (next_pf_time
!= MaxTick
)
843 schedMemSideSendEvent(next_pf_time
);
849 // See comment in cache.hh.
851 Cache::getBusPacket(PacketPtr cpu_pkt
, CacheBlk
*blk
,
852 bool needsExclusive
) const
854 bool blkValid
= blk
&& blk
->isValid();
856 if (cpu_pkt
->req
->isUncacheable()) {
857 // note that at the point we see the uncacheable request we
858 // flush any block, but there could be an outstanding MSHR,
859 // and the cache could have filled again before we actually
860 // send out the forwarded uncacheable request (blk could thus
866 (cpu_pkt
->isUpgrade() ||
867 cpu_pkt
->evictingBlock())) {
868 // Writebacks that weren't allocated in access() and upgrades
869 // from upper-level caches that missed completely just go
874 assert(cpu_pkt
->needsResponse());
877 // @TODO make useUpgrades a parameter.
878 // Note that ownership protocols require upgrade, otherwise a
879 // write miss on a shared owned block will generate a ReadExcl,
880 // which will clobber the owned copy.
881 const bool useUpgrades
= true;
882 if (blkValid
&& useUpgrades
) {
883 // only reason to be here is that blk is shared
884 // (read-only) and we need exclusive
885 assert(needsExclusive
);
886 assert(!blk
->isWritable());
887 cmd
= cpu_pkt
->isLLSC() ? MemCmd::SCUpgradeReq
: MemCmd::UpgradeReq
;
888 } else if (cpu_pkt
->cmd
== MemCmd::SCUpgradeFailReq
||
889 cpu_pkt
->cmd
== MemCmd::StoreCondFailReq
) {
890 // Even though this SC will fail, we still need to send out the
891 // request and get the data to supply it to other snoopers in the case
892 // where the determination the StoreCond fails is delayed due to
893 // all caches not being on the same local bus.
894 cmd
= MemCmd::SCUpgradeFailReq
;
895 } else if (cpu_pkt
->cmd
== MemCmd::WriteLineReq
) {
896 // forward as invalidate to all other caches, this gives us
897 // the line in exclusive state, and invalidates all other
899 cmd
= MemCmd::InvalidateReq
;
902 cmd
= needsExclusive
? MemCmd::ReadExReq
:
903 (isReadOnly
? MemCmd::ReadCleanReq
: MemCmd::ReadSharedReq
);
905 PacketPtr pkt
= new Packet(cpu_pkt
->req
, cmd
, blkSize
);
907 // if there are sharers in the upper levels, pass that info downstream
908 if (cpu_pkt
->sharedAsserted()) {
909 // note that cpu_pkt may have spent a considerable time in the
910 // MSHR queue and that the information could possibly be out
911 // of date, however, there is no harm in conservatively
912 // assuming the block is shared
914 DPRINTF(Cache
, "%s passing shared from %s to %s addr %#llx size %d\n",
915 __func__
, cpu_pkt
->cmdString(), pkt
->cmdString(),
916 pkt
->getAddr(), pkt
->getSize());
919 // the packet should be block aligned
920 assert(pkt
->getAddr() == blockAlign(pkt
->getAddr()));
923 DPRINTF(Cache
, "%s created %s from %s for addr %#llx size %d\n",
924 __func__
, pkt
->cmdString(), cpu_pkt
->cmdString(), pkt
->getAddr(),
931 Cache::recvAtomic(PacketPtr pkt
)
933 // We are in atomic mode so we pay just for lookupLatency here.
934 Cycles lat
= lookupLatency
;
935 // @TODO: make this a parameter
936 bool last_level_cache
= false;
938 // Forward the request if the system is in cache bypass mode.
939 if (system
->bypassCaches())
940 return ticksToCycles(memSidePort
->sendAtomic(pkt
));
942 promoteWholeLineWrites(pkt
);
944 if (pkt
->memInhibitAsserted()) {
945 // have to invalidate ourselves and any lower caches even if
946 // upper cache will be responding
947 if (pkt
->isInvalidate()) {
948 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
949 if (blk
&& blk
->isValid()) {
950 tags
->invalidate(blk
);
952 DPRINTF(Cache
, "rcvd mem-inhibited %s on %#llx (%s):"
954 pkt
->cmdString(), pkt
->getAddr(),
955 pkt
->isSecure() ? "s" : "ns");
957 if (!last_level_cache
) {
958 DPRINTF(Cache
, "forwarding mem-inhibited %s on %#llx (%s)\n",
959 pkt
->cmdString(), pkt
->getAddr(),
960 pkt
->isSecure() ? "s" : "ns");
961 lat
+= ticksToCycles(memSidePort
->sendAtomic(pkt
));
964 DPRINTF(Cache
, "rcvd mem-inhibited %s on %#llx: not responding\n",
965 pkt
->cmdString(), pkt
->getAddr());
968 return lat
* clockPeriod();
971 // should assert here that there are no outstanding MSHRs or
972 // writebacks... that would mean that someone used an atomic
973 // access in timing mode
975 CacheBlk
*blk
= NULL
;
976 PacketList writebacks
;
977 bool satisfied
= access(pkt
, blk
, lat
, writebacks
);
979 // handle writebacks resulting from the access here to ensure they
980 // logically proceed anything happening below
981 while (!writebacks
.empty()){
982 PacketPtr wbPkt
= writebacks
.front();
983 memSidePort
->sendAtomic(wbPkt
);
984 writebacks
.pop_front();
991 PacketPtr bus_pkt
= getBusPacket(pkt
, blk
, pkt
->needsExclusive());
993 bool is_forward
= (bus_pkt
== NULL
);
996 // just forwarding the same request to the next level
997 // no local cache operation involved
1001 DPRINTF(Cache
, "Sending an atomic %s for %#llx (%s)\n",
1002 bus_pkt
->cmdString(), bus_pkt
->getAddr(),
1003 bus_pkt
->isSecure() ? "s" : "ns");
1006 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1009 lat
+= ticksToCycles(memSidePort
->sendAtomic(bus_pkt
));
1011 // We are now dealing with the response handling
1012 DPRINTF(Cache
, "Receive response: %s for addr %#llx (%s) in state %i\n",
1013 bus_pkt
->cmdString(), bus_pkt
->getAddr(),
1014 bus_pkt
->isSecure() ? "s" : "ns",
1017 // If packet was a forward, the response (if any) is already
1018 // in place in the bus_pkt == pkt structure, so we don't need
1019 // to do anything. Otherwise, use the separate bus_pkt to
1020 // generate response to pkt and then delete it.
1022 if (pkt
->needsResponse()) {
1023 assert(bus_pkt
->isResponse());
1024 if (bus_pkt
->isError()) {
1025 pkt
->makeAtomicResponse();
1026 pkt
->copyError(bus_pkt
);
1027 } else if (pkt
->cmd
== MemCmd::InvalidateReq
) {
1029 // invalidate response to a cache that received
1030 // an invalidate request
1031 satisfyCpuSideRequest(pkt
, blk
);
1033 } else if (pkt
->cmd
== MemCmd::WriteLineReq
) {
1034 // note the use of pkt, not bus_pkt here.
1036 // write-line request to the cache that promoted
1037 // the write to a whole line
1038 blk
= handleFill(pkt
, blk
, writebacks
);
1039 satisfyCpuSideRequest(pkt
, blk
);
1040 } else if (bus_pkt
->isRead() ||
1041 bus_pkt
->cmd
== MemCmd::UpgradeResp
) {
1042 // we're updating cache state to allow us to
1043 // satisfy the upstream request from the cache
1044 blk
= handleFill(bus_pkt
, blk
, writebacks
);
1045 satisfyCpuSideRequest(pkt
, blk
);
1047 // we're satisfying the upstream request without
1048 // modifying cache state, e.g., a write-through
1049 pkt
->makeAtomicResponse();
1056 // Note that we don't invoke the prefetcher at all in atomic mode.
1057 // It's not clear how to do it properly, particularly for
1058 // prefetchers that aggressively generate prefetch candidates and
1059 // rely on bandwidth contention to throttle them; these will tend
1060 // to pollute the cache in atomic mode since there is no bandwidth
1061 // contention. If we ever do want to enable prefetching in atomic
1062 // mode, though, this is the place to do it... see timingAccess()
1063 // for an example (though we'd want to issue the prefetch(es)
1064 // immediately rather than calling requestMemSideBus() as we do
1067 // Handle writebacks (from the response handling) if needed
1068 while (!writebacks
.empty()){
1069 PacketPtr wbPkt
= writebacks
.front();
1070 memSidePort
->sendAtomic(wbPkt
);
1071 writebacks
.pop_front();
1075 if (pkt
->needsResponse()) {
1076 pkt
->makeAtomicResponse();
1079 return lat
* clockPeriod();
1084 Cache::functionalAccess(PacketPtr pkt
, bool fromCpuSide
)
1086 if (system
->bypassCaches()) {
1087 // Packets from the memory side are snoop request and
1088 // shouldn't happen in bypass mode.
1089 assert(fromCpuSide
);
1091 // The cache should be flushed if we are in cache bypass mode,
1092 // so we don't need to check if we need to update anything.
1093 memSidePort
->sendFunctional(pkt
);
1097 Addr blk_addr
= blockAlign(pkt
->getAddr());
1098 bool is_secure
= pkt
->isSecure();
1099 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
1100 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
1102 pkt
->pushLabel(name());
1104 CacheBlkPrintWrapper
cbpw(blk
);
1106 // Note that just because an L2/L3 has valid data doesn't mean an
1107 // L1 doesn't have a more up-to-date modified copy that still
1108 // needs to be found. As a result we always update the request if
1109 // we have it, but only declare it satisfied if we are the owner.
1111 // see if we have data at all (owned or otherwise)
1112 bool have_data
= blk
&& blk
->isValid()
1113 && pkt
->checkFunctional(&cbpw
, blk_addr
, is_secure
, blkSize
,
1116 // data we have is dirty if marked as such or if valid & ownership
1117 // pending due to outstanding UpgradeReq
1119 have_data
&& (blk
->isDirty() ||
1120 (mshr
&& mshr
->inService
&& mshr
->isPendingDirty()));
1122 bool done
= have_dirty
1123 || cpuSidePort
->checkFunctional(pkt
)
1124 || mshrQueue
.checkFunctional(pkt
, blk_addr
)
1125 || writeBuffer
.checkFunctional(pkt
, blk_addr
)
1126 || memSidePort
->checkFunctional(pkt
);
1128 DPRINTF(Cache
, "functional %s %#llx (%s) %s%s%s\n",
1129 pkt
->cmdString(), pkt
->getAddr(), is_secure
? "s" : "ns",
1130 (blk
&& blk
->isValid()) ? "valid " : "",
1131 have_data
? "data " : "", done
? "done " : "");
1133 // We're leaving the cache, so pop cache->name() label
1137 pkt
->makeResponse();
1139 // if it came as a request from the CPU side then make sure it
1140 // continues towards the memory side
1142 memSidePort
->sendFunctional(pkt
);
1143 } else if (forwardSnoops
&& cpuSidePort
->isSnooping()) {
1144 // if it came from the memory side, it must be a snoop request
1145 // and we should only forward it if we are forwarding snoops
1146 cpuSidePort
->sendFunctionalSnoop(pkt
);
1152 /////////////////////////////////////////////////////
1154 // Response handling: responses from the memory side
1156 /////////////////////////////////////////////////////
1160 Cache::recvTimingResp(PacketPtr pkt
)
1162 assert(pkt
->isResponse());
1164 // all header delay should be paid for by the crossbar, unless
1165 // this is a prefetch response from above
1166 panic_if(pkt
->headerDelay
!= 0 && pkt
->cmd
!= MemCmd::HardPFResp
,
1167 "%s saw a non-zero packet delay\n", name());
1169 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->senderState
);
1170 bool is_error
= pkt
->isError();
1175 DPRINTF(Cache
, "Cache received packet with error for addr %#llx (%s), "
1176 "cmd: %s\n", pkt
->getAddr(), pkt
->isSecure() ? "s" : "ns",
1180 DPRINTF(Cache
, "Handling response %s for addr %#llx size %d (%s)\n",
1181 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize(),
1182 pkt
->isSecure() ? "s" : "ns");
1184 MSHRQueue
*mq
= mshr
->queue
;
1185 bool wasFull
= mq
->isFull();
1187 if (mshr
== noTargetMSHR
) {
1188 // we always clear at least one target
1189 clearBlocked(Blocked_NoTargets
);
1190 noTargetMSHR
= NULL
;
1193 // Initial target is used just for stats
1194 MSHR::Target
*initial_tgt
= mshr
->getTarget();
1195 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
1196 int stats_cmd_idx
= initial_tgt
->pkt
->cmdToIndex();
1197 Tick miss_latency
= curTick() - initial_tgt
->recvTime
;
1198 PacketList writebacks
;
1199 // We need forward_time here because we have a call of
1200 // allocateWriteBuffer() that need this parameter to specify the
1201 // time to request the bus. In this case we use forward latency
1202 // because there is a writeback. We pay also here for headerDelay
1203 // that is charged of bus latencies if the packet comes from the
1205 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
1207 if (pkt
->req
->isUncacheable()) {
1208 assert(pkt
->req
->masterId() < system
->maxMasters());
1209 mshr_uncacheable_lat
[stats_cmd_idx
][pkt
->req
->masterId()] +=
1212 assert(pkt
->req
->masterId() < system
->maxMasters());
1213 mshr_miss_latency
[stats_cmd_idx
][pkt
->req
->masterId()] +=
1217 bool is_fill
= !mshr
->isForward
&&
1218 (pkt
->isRead() || pkt
->cmd
== MemCmd::UpgradeResp
);
1220 if (is_fill
&& !is_error
) {
1221 DPRINTF(Cache
, "Block for addr %#llx being updated in Cache\n",
1224 // give mshr a chance to do some dirty work
1225 mshr
->handleFill(pkt
, blk
);
1227 blk
= handleFill(pkt
, blk
, writebacks
);
1228 assert(blk
!= NULL
);
1231 // allow invalidation responses originating from write-line
1232 // requests to be discarded
1233 bool discard_invalidate
= false;
1235 // First offset for critical word first calculations
1236 int initial_offset
= initial_tgt
->pkt
->getOffset(blkSize
);
1238 while (mshr
->hasTargets()) {
1239 MSHR::Target
*target
= mshr
->getTarget();
1240 Packet
*tgt_pkt
= target
->pkt
;
1242 switch (target
->source
) {
1243 case MSHR::Target::FromCPU
:
1244 Tick completion_time
;
1245 // Here we charge on completion_time the delay of the xbar if the
1246 // packet comes from it, charged on headerDelay.
1247 completion_time
= pkt
->headerDelay
;
1249 // Software prefetch handling for cache closest to core
1250 if (tgt_pkt
->cmd
.isSWPrefetch()) {
1251 // a software prefetch would have already been ack'd immediately
1252 // with dummy data so the core would be able to retire it.
1253 // this request completes right here, so we deallocate it.
1254 delete tgt_pkt
->req
;
1256 break; // skip response
1259 // unlike the other packet flows, where data is found in other
1260 // caches or memory and brought back, write-line requests always
1261 // have the data right away, so the above check for "is fill?"
1262 // cannot actually be determined until examining the stored MSHR
1263 // state. We "catch up" with that logic here, which is duplicated
1265 if (tgt_pkt
->cmd
== MemCmd::WriteLineReq
) {
1268 // NB: we use the original packet here and not the response!
1269 mshr
->handleFill(tgt_pkt
, blk
);
1270 blk
= handleFill(tgt_pkt
, blk
, writebacks
);
1271 assert(blk
!= NULL
);
1273 // treat as a fill, and discard the invalidation
1276 discard_invalidate
= true;
1280 satisfyCpuSideRequest(tgt_pkt
, blk
,
1281 true, mshr
->hasPostDowngrade());
1283 // How many bytes past the first request is this one
1284 int transfer_offset
=
1285 tgt_pkt
->getOffset(blkSize
) - initial_offset
;
1286 if (transfer_offset
< 0) {
1287 transfer_offset
+= blkSize
;
1290 // If not critical word (offset) return payloadDelay.
1291 // responseLatency is the latency of the return path
1292 // from lower level caches/memory to an upper level cache or
1294 completion_time
+= clockEdge(responseLatency
) +
1295 (transfer_offset
? pkt
->payloadDelay
: 0);
1297 assert(!tgt_pkt
->req
->isUncacheable());
1299 assert(tgt_pkt
->req
->masterId() < system
->maxMasters());
1300 missLatency
[tgt_pkt
->cmdToIndex()][tgt_pkt
->req
->masterId()] +=
1301 completion_time
- target
->recvTime
;
1302 } else if (pkt
->cmd
== MemCmd::UpgradeFailResp
) {
1303 // failed StoreCond upgrade
1304 assert(tgt_pkt
->cmd
== MemCmd::StoreCondReq
||
1305 tgt_pkt
->cmd
== MemCmd::StoreCondFailReq
||
1306 tgt_pkt
->cmd
== MemCmd::SCUpgradeFailReq
);
1307 // responseLatency is the latency of the return path
1308 // from lower level caches/memory to an upper level cache or
1310 completion_time
+= clockEdge(responseLatency
) +
1312 tgt_pkt
->req
->setExtraData(0);
1314 // not a cache fill, just forwarding response
1315 // responseLatency is the latency of the return path
1316 // from lower level cahces/memory to the core.
1317 completion_time
+= clockEdge(responseLatency
) +
1319 if (pkt
->isRead() && !is_error
) {
1321 assert(pkt
->getAddr() == tgt_pkt
->getAddr());
1322 assert(pkt
->getSize() >= tgt_pkt
->getSize());
1324 tgt_pkt
->setData(pkt
->getConstPtr
<uint8_t>());
1327 tgt_pkt
->makeTimingResponse();
1328 // if this packet is an error copy that to the new packet
1330 tgt_pkt
->copyError(pkt
);
1331 if (tgt_pkt
->cmd
== MemCmd::ReadResp
&&
1332 (pkt
->isInvalidate() || mshr
->hasPostInvalidate())) {
1333 // If intermediate cache got ReadRespWithInvalidate,
1334 // propagate that. Response should not have
1335 // isInvalidate() set otherwise.
1336 tgt_pkt
->cmd
= MemCmd::ReadRespWithInvalidate
;
1337 DPRINTF(Cache
, "%s updated cmd to %s for addr %#llx\n",
1338 __func__
, tgt_pkt
->cmdString(), tgt_pkt
->getAddr());
1340 // Reset the bus additional time as it is now accounted for
1341 tgt_pkt
->headerDelay
= tgt_pkt
->payloadDelay
= 0;
1342 cpuSidePort
->schedTimingResp(tgt_pkt
, completion_time
);
1345 case MSHR::Target::FromPrefetcher
:
1346 assert(tgt_pkt
->cmd
== MemCmd::HardPFReq
);
1348 blk
->status
|= BlkHWPrefetched
;
1349 delete tgt_pkt
->req
;
1353 case MSHR::Target::FromSnoop
:
1354 // I don't believe that a snoop can be in an error state
1356 // response to snoop request
1357 DPRINTF(Cache
, "processing deferred snoop...\n");
1358 assert(!(pkt
->isInvalidate() && !mshr
->hasPostInvalidate()));
1359 handleSnoop(tgt_pkt
, blk
, true, true, mshr
->hasPostInvalidate());
1363 panic("Illegal target->source enum %d\n", target
->source
);
1369 if (blk
&& blk
->isValid()) {
1370 // an invalidate response stemming from a write line request
1371 // should not invalidate the block, so check if the
1372 // invalidation should be discarded
1373 if ((pkt
->isInvalidate() || mshr
->hasPostInvalidate()) &&
1374 !discard_invalidate
) {
1375 assert(blk
!= tempBlock
);
1376 tags
->invalidate(blk
);
1378 } else if (mshr
->hasPostDowngrade()) {
1379 blk
->status
&= ~BlkWritable
;
1383 if (mshr
->promoteDeferredTargets()) {
1384 // avoid later read getting stale data while write miss is
1385 // outstanding.. see comment in timingAccess()
1387 blk
->status
&= ~BlkReadable
;
1390 mq
->markPending(mshr
);
1391 schedMemSideSendEvent(clockEdge() + pkt
->payloadDelay
);
1393 mq
->deallocate(mshr
);
1394 if (wasFull
&& !mq
->isFull()) {
1395 clearBlocked((BlockedCause
)mq
->index
);
1398 // Request the bus for a prefetch if this deallocation freed enough
1399 // MSHRs for a prefetch to take place
1400 if (prefetcher
&& mq
== &mshrQueue
&& mshrQueue
.canPrefetch()) {
1401 Tick next_pf_time
= std::max(prefetcher
->nextPrefetchReadyTime(),
1403 if (next_pf_time
!= MaxTick
)
1404 schedMemSideSendEvent(next_pf_time
);
1407 // reset the xbar additional timinig as it is now accounted for
1408 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
1410 // copy writebacks to write buffer
1411 doWritebacks(writebacks
, forward_time
);
1413 // if we used temp block, check to see if its valid and then clear it out
1414 if (blk
== tempBlock
&& tempBlock
->isValid()) {
1415 // We use forwardLatency here because we are copying
1416 // Writebacks/CleanEvicts to write buffer. It specifies the latency to
1417 // allocate an internal buffer and to schedule an event to the
1419 if (blk
->isDirty()) {
1420 PacketPtr wbPkt
= writebackBlk(blk
);
1421 allocateWriteBuffer(wbPkt
, forward_time
);
1422 // Set BLOCK_CACHED flag if cached above.
1423 if (isCachedAbove(wbPkt
))
1424 wbPkt
->setBlockCached();
1426 PacketPtr wcPkt
= cleanEvictBlk(blk
);
1427 // Check to see if block is cached above. If not allocate
1429 if (isCachedAbove(wcPkt
))
1432 allocateWriteBuffer(wcPkt
, forward_time
);
1437 DPRINTF(Cache
, "Leaving %s with %s for addr %#llx\n", __func__
,
1438 pkt
->cmdString(), pkt
->getAddr());
1443 Cache::writebackBlk(CacheBlk
*blk
)
1445 chatty_assert(!isReadOnly
, "Writeback from read-only cache");
1446 assert(blk
&& blk
->isValid() && blk
->isDirty());
1448 writebacks
[Request::wbMasterId
]++;
1450 Request
*writebackReq
=
1451 new Request(tags
->regenerateBlkAddr(blk
->tag
, blk
->set
), blkSize
, 0,
1452 Request::wbMasterId
);
1453 if (blk
->isSecure())
1454 writebackReq
->setFlags(Request::SECURE
);
1456 writebackReq
->taskId(blk
->task_id
);
1457 blk
->task_id
= ContextSwitchTaskId::Unknown
;
1458 blk
->tickInserted
= curTick();
1460 PacketPtr writeback
= new Packet(writebackReq
, MemCmd::Writeback
);
1461 if (blk
->isWritable()) {
1462 // not asserting shared means we pass the block in modified
1463 // state, mark our own block non-writeable
1464 blk
->status
&= ~BlkWritable
;
1466 // we are in the owned state, tell the receiver
1467 writeback
->assertShared();
1470 writeback
->allocate();
1471 std::memcpy(writeback
->getPtr
<uint8_t>(), blk
->data
, blkSize
);
1473 blk
->status
&= ~BlkDirty
;
1478 Cache::cleanEvictBlk(CacheBlk
*blk
)
1480 assert(blk
&& blk
->isValid() && !blk
->isDirty());
1481 // Creating a zero sized write, a message to the snoop filter
1483 new Request(tags
->regenerateBlkAddr(blk
->tag
, blk
->set
), blkSize
, 0,
1484 Request::wbMasterId
);
1485 if (blk
->isSecure())
1486 req
->setFlags(Request::SECURE
);
1488 req
->taskId(blk
->task_id
);
1489 blk
->task_id
= ContextSwitchTaskId::Unknown
;
1490 blk
->tickInserted
= curTick();
1492 PacketPtr pkt
= new Packet(req
, MemCmd::CleanEvict
);
1494 DPRINTF(Cache
, "%s%s %x Create CleanEvict\n", pkt
->cmdString(),
1495 pkt
->req
->isInstFetch() ? " (ifetch)" : "",
1502 Cache::memWriteback()
1504 CacheBlkVisitorWrapper
visitor(*this, &Cache::writebackVisitor
);
1505 tags
->forEachBlk(visitor
);
1509 Cache::memInvalidate()
1511 CacheBlkVisitorWrapper
visitor(*this, &Cache::invalidateVisitor
);
1512 tags
->forEachBlk(visitor
);
1516 Cache::isDirty() const
1518 CacheBlkIsDirtyVisitor visitor
;
1519 tags
->forEachBlk(visitor
);
1521 return visitor
.isDirty();
1525 Cache::writebackVisitor(CacheBlk
&blk
)
1527 if (blk
.isDirty()) {
1528 assert(blk
.isValid());
1530 Request
request(tags
->regenerateBlkAddr(blk
.tag
, blk
.set
),
1531 blkSize
, 0, Request::funcMasterId
);
1532 request
.taskId(blk
.task_id
);
1534 Packet
packet(&request
, MemCmd::WriteReq
);
1535 packet
.dataStatic(blk
.data
);
1537 memSidePort
->sendFunctional(&packet
);
1539 blk
.status
&= ~BlkDirty
;
1546 Cache::invalidateVisitor(CacheBlk
&blk
)
1550 warn_once("Invalidating dirty cache lines. Expect things to break.\n");
1552 if (blk
.isValid()) {
1553 assert(!blk
.isDirty());
1554 tags
->invalidate(&blk
);
1562 Cache::allocateBlock(Addr addr
, bool is_secure
, PacketList
&writebacks
)
1564 CacheBlk
*blk
= tags
->findVictim(addr
);
1566 // It is valid to return NULL if there is no victim
1570 if (blk
->isValid()) {
1571 Addr repl_addr
= tags
->regenerateBlkAddr(blk
->tag
, blk
->set
);
1572 MSHR
*repl_mshr
= mshrQueue
.findMatch(repl_addr
, blk
->isSecure());
1574 // must be an outstanding upgrade request
1575 // on a block we're about to replace...
1576 assert(!blk
->isWritable() || blk
->isDirty());
1577 assert(repl_mshr
->needsExclusive());
1578 // too hard to replace block with transient state
1579 // allocation failed, block not inserted
1582 DPRINTF(Cache
, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n",
1583 repl_addr
, blk
->isSecure() ? "s" : "ns",
1584 addr
, is_secure
? "s" : "ns",
1585 blk
->isDirty() ? "writeback" : "clean");
1587 // Will send up Writeback/CleanEvict snoops via isCachedAbove
1588 // when pushing this writeback list into the write buffer.
1589 if (blk
->isDirty()) {
1590 // Save writeback packet for handling by caller
1591 writebacks
.push_back(writebackBlk(blk
));
1593 writebacks
.push_back(cleanEvictBlk(blk
));
1602 // Note that the reason we return a list of writebacks rather than
1603 // inserting them directly in the write buffer is that this function
1604 // is called by both atomic and timing-mode accesses, and in atomic
1605 // mode we don't mess with the write buffer (we just perform the
1606 // writebacks atomically once the original request is complete).
1608 Cache::handleFill(PacketPtr pkt
, CacheBlk
*blk
, PacketList
&writebacks
)
1610 assert(pkt
->isResponse() || pkt
->cmd
== MemCmd::WriteLineReq
);
1611 Addr addr
= pkt
->getAddr();
1612 bool is_secure
= pkt
->isSecure();
1614 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1617 // When handling a fill, discard any CleanEvicts for the
1618 // same address in write buffer.
1619 Addr M5_VAR_USED blk_addr
= blockAlign(pkt
->getAddr());
1620 std::vector
<MSHR
*> M5_VAR_USED wbs
;
1621 assert (!writeBuffer
.findMatches(blk_addr
, is_secure
, wbs
));
1624 // better have read new data...
1625 assert(pkt
->hasData());
1627 // only read responses and write-line requests have data;
1628 // note that we don't write the data here for write-line - that
1629 // happens in the subsequent satisfyCpuSideRequest.
1630 assert(pkt
->isRead() || pkt
->cmd
== MemCmd::WriteLineReq
);
1632 // need to do a replacement
1633 blk
= allocateBlock(addr
, is_secure
, writebacks
);
1635 // No replaceable block... just use temporary storage to
1636 // complete the current request and then get rid of it
1637 assert(!tempBlock
->isValid());
1639 tempBlock
->set
= tags
->extractSet(addr
);
1640 tempBlock
->tag
= tags
->extractTag(addr
);
1641 // @todo: set security state as well...
1642 DPRINTF(Cache
, "using temp block for %#llx (%s)\n", addr
,
1643 is_secure
? "s" : "ns");
1645 tags
->insertBlock(pkt
, blk
);
1648 // we should never be overwriting a valid block
1649 assert(!blk
->isValid());
1651 // existing block... probably an upgrade
1652 assert(blk
->tag
== tags
->extractTag(addr
));
1653 // either we're getting new data or the block should already be valid
1654 assert(pkt
->hasData() || blk
->isValid());
1655 // don't clear block status... if block is already dirty we
1656 // don't want to lose that
1660 blk
->status
|= BlkSecure
;
1661 blk
->status
|= BlkValid
| BlkReadable
;
1663 if (!pkt
->sharedAsserted()) {
1664 // we could get non-shared responses from memory (rather than
1665 // a cache) even in a read-only cache, note that we set this
1666 // bit even for a read-only cache as we use it to represent
1667 // the exclusive state
1668 blk
->status
|= BlkWritable
;
1670 // If we got this via cache-to-cache transfer (i.e., from a
1671 // cache that was an owner) and took away that owner's copy,
1672 // then we need to write it back. Normally this happens
1673 // anyway as a side effect of getting a copy to write it, but
1674 // there are cases (such as failed store conditionals or
1675 // compare-and-swaps) where we'll demand an exclusive copy but
1676 // end up not writing it.
1677 if (pkt
->memInhibitAsserted()) {
1678 blk
->status
|= BlkDirty
;
1680 chatty_assert(!isReadOnly
, "Should never see dirty snoop response "
1681 "in read-only cache %s\n", name());
1685 DPRINTF(Cache
, "Block addr %#llx (%s) moving from state %x to %s\n",
1686 addr
, is_secure
? "s" : "ns", old_state
, blk
->print());
1688 // if we got new data, copy it in (checking for a read response
1689 // and a response that has data is the same in the end)
1690 if (pkt
->isRead()) {
1692 assert(pkt
->hasData());
1693 assert(pkt
->getSize() == blkSize
);
1695 std::memcpy(blk
->data
, pkt
->getConstPtr
<uint8_t>(), blkSize
);
1697 // We pay for fillLatency here.
1698 blk
->whenReady
= clockEdge() + fillLatency
* clockPeriod() +
1705 /////////////////////////////////////////////////////
1707 // Snoop path: requests coming in from the memory side
1709 /////////////////////////////////////////////////////
1712 Cache::doTimingSupplyResponse(PacketPtr req_pkt
, const uint8_t *blk_data
,
1713 bool already_copied
, bool pending_inval
)
1716 assert(req_pkt
->isRequest());
1717 assert(req_pkt
->needsResponse());
1719 DPRINTF(Cache
, "%s for %s addr %#llx size %d\n", __func__
,
1720 req_pkt
->cmdString(), req_pkt
->getAddr(), req_pkt
->getSize());
1721 // timing-mode snoop responses require a new packet, unless we
1722 // already made a copy...
1723 PacketPtr pkt
= req_pkt
;
1724 if (!already_copied
)
1725 // do not clear flags, and allocate space for data if the
1726 // packet needs it (the only packets that carry data are read
1728 pkt
= new Packet(req_pkt
, false, req_pkt
->isRead());
1730 assert(req_pkt
->req
->isUncacheable() || req_pkt
->isInvalidate() ||
1731 pkt
->sharedAsserted());
1732 pkt
->makeTimingResponse();
1733 if (pkt
->isRead()) {
1734 pkt
->setDataFromBlock(blk_data
, blkSize
);
1736 if (pkt
->cmd
== MemCmd::ReadResp
&& pending_inval
) {
1737 // Assume we defer a response to a read from a far-away cache
1738 // A, then later defer a ReadExcl from a cache B on the same
1739 // bus as us. We'll assert MemInhibit in both cases, but in
1740 // the latter case MemInhibit will keep the invalidation from
1741 // reaching cache A. This special response tells cache A that
1742 // it gets the block to satisfy its read, but must immediately
1744 pkt
->cmd
= MemCmd::ReadRespWithInvalidate
;
1746 // Here we consider forward_time, paying for just forward latency and
1747 // also charging the delay provided by the xbar.
1748 // forward_time is used as send_time in next allocateWriteBuffer().
1749 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
1750 // Here we reset the timing of the packet.
1751 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
1752 DPRINTF(Cache
, "%s created response: %s addr %#llx size %d tick: %lu\n",
1753 __func__
, pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize(),
1755 memSidePort
->schedTimingSnoopResp(pkt
, forward_time
, true);
1759 Cache::handleSnoop(PacketPtr pkt
, CacheBlk
*blk
, bool is_timing
,
1760 bool is_deferred
, bool pending_inval
)
1762 DPRINTF(Cache
, "%s for %s addr %#llx size %d\n", __func__
,
1763 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
1764 // deferred snoops can only happen in timing mode
1765 assert(!(is_deferred
&& !is_timing
));
1766 // pending_inval only makes sense on deferred snoops
1767 assert(!(pending_inval
&& !is_deferred
));
1768 assert(pkt
->isRequest());
1770 // the packet may get modified if we or a forwarded snooper
1771 // responds in atomic mode, so remember a few things about the
1772 // original packet up front
1773 bool invalidate
= pkt
->isInvalidate();
1774 bool M5_VAR_USED needs_exclusive
= pkt
->needsExclusive();
1776 if (forwardSnoops
) {
1777 // first propagate snoop upward to see if anyone above us wants to
1778 // handle it. save & restore packet src since it will get
1779 // rewritten to be relative to cpu-side bus (if any)
1780 bool alreadyResponded
= pkt
->memInhibitAsserted();
1782 // copy the packet so that we can clear any flags before
1783 // forwarding it upwards, we also allocate data (passing
1784 // the pointer along in case of static data), in case
1785 // there is a snoop hit in upper levels
1786 Packet
snoopPkt(pkt
, true, true);
1787 snoopPkt
.setExpressSnoop();
1788 snoopPkt
.pushSenderState(new ForwardResponseRecord());
1789 // the snoop packet does not need to wait any additional
1791 snoopPkt
.headerDelay
= snoopPkt
.payloadDelay
= 0;
1792 cpuSidePort
->sendTimingSnoopReq(&snoopPkt
);
1793 if (snoopPkt
.memInhibitAsserted()) {
1794 // cache-to-cache response from some upper cache
1795 assert(!alreadyResponded
);
1796 pkt
->assertMemInhibit();
1798 // no cache (or anyone else for that matter) will
1799 // respond, so delete the ForwardResponseRecord here
1800 delete snoopPkt
.popSenderState();
1802 if (snoopPkt
.sharedAsserted()) {
1803 pkt
->assertShared();
1805 // If this request is a prefetch or clean evict and an upper level
1806 // signals block present, make sure to propagate the block
1807 // presence to the requester.
1808 if (snoopPkt
.isBlockCached()) {
1809 pkt
->setBlockCached();
1812 cpuSidePort
->sendAtomicSnoop(pkt
);
1813 if (!alreadyResponded
&& pkt
->memInhibitAsserted()) {
1814 // cache-to-cache response from some upper cache:
1815 // forward response to original requester
1816 assert(pkt
->isResponse());
1821 if (!blk
|| !blk
->isValid()) {
1822 DPRINTF(Cache
, "%s snoop miss for %s addr %#llx size %d\n",
1823 __func__
, pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
1826 DPRINTF(Cache
, "%s snoop hit for %s for addr %#llx size %d, "
1827 "old state is %s\n", __func__
, pkt
->cmdString(),
1828 pkt
->getAddr(), pkt
->getSize(), blk
->print());
1831 chatty_assert(!(isReadOnly
&& blk
->isDirty()),
1832 "Should never have a dirty block in a read-only cache %s\n",
1835 // We may end up modifying both the block state and the packet (if
1836 // we respond in atomic mode), so just figure out what to do now
1837 // and then do it later. If we find dirty data while snooping for
1838 // an invalidate, we don't need to send a response. The
1839 // invalidation itself is taken care of below.
1840 bool respond
= blk
->isDirty() && pkt
->needsResponse() &&
1841 pkt
->cmd
!= MemCmd::InvalidateReq
;
1842 bool have_exclusive
= blk
->isWritable();
1844 // Invalidate any prefetch's from below that would strip write permissions
1845 // MemCmd::HardPFReq is only observed by upstream caches. After missing
1846 // above and in it's own cache, a new MemCmd::ReadReq is created that
1847 // downstream caches observe.
1848 if (pkt
->mustCheckAbove()) {
1849 DPRINTF(Cache
, "Found addr %#llx in upper level cache for snoop %s from"
1850 " lower cache\n", pkt
->getAddr(), pkt
->cmdString());
1851 pkt
->setBlockCached();
1855 if (!pkt
->req
->isUncacheable() && pkt
->isRead() && !invalidate
) {
1856 assert(!needs_exclusive
);
1857 pkt
->assertShared();
1858 int bits_to_clear
= BlkWritable
;
1859 const bool haveOwnershipState
= true; // for now
1860 if (!haveOwnershipState
) {
1861 // if we don't support pure ownership (dirty && !writable),
1862 // have to clear dirty bit here, assume memory snarfs data
1863 // on cache-to-cache xfer
1864 bits_to_clear
|= BlkDirty
;
1866 blk
->status
&= ~bits_to_clear
;
1870 // prevent anyone else from responding, cache as well as
1871 // memory, and also prevent any memory from even seeing the
1872 // request (with current inhibited semantics), note that this
1873 // applies both to reads and writes and that for writes it
1874 // works thanks to the fact that we still have dirty data and
1875 // will write it back at a later point
1876 pkt
->assertMemInhibit();
1877 if (have_exclusive
) {
1878 // in the case of an uncacheable request there is no need
1879 // to set the exclusive flag, but since the recipient does
1880 // not care there is no harm in doing so
1881 pkt
->setSupplyExclusive();
1884 doTimingSupplyResponse(pkt
, blk
->data
, is_deferred
, pending_inval
);
1886 pkt
->makeAtomicResponse();
1887 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1891 if (!respond
&& is_timing
&& is_deferred
) {
1892 // if it's a deferred timing snoop then we've made a copy of
1893 // both the request and the packet, and so if we're not using
1894 // those copies to respond and delete them here
1895 DPRINTF(Cache
, "Deleting pkt %p and request %p for cmd %s addr: %p\n",
1896 pkt
, pkt
->req
, pkt
->cmdString(), pkt
->getAddr());
1898 // the packets needs a response (just not from us), so we also
1899 // need to delete the request and not rely on the packet
1901 assert(pkt
->needsResponse());
1906 // Do this last in case it deallocates block data or something
1909 if (blk
!= tempBlock
)
1910 tags
->invalidate(blk
);
1914 DPRINTF(Cache
, "new state is %s\n", blk
->print());
1919 Cache::recvTimingSnoopReq(PacketPtr pkt
)
1921 DPRINTF(Cache
, "%s for %s addr %#llx size %d\n", __func__
,
1922 pkt
->cmdString(), pkt
->getAddr(), pkt
->getSize());
1924 // Snoops shouldn't happen when bypassing caches
1925 assert(!system
->bypassCaches());
1927 // no need to snoop writebacks or requests that are not in range
1928 if (!inRange(pkt
->getAddr())) {
1932 bool is_secure
= pkt
->isSecure();
1933 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
1935 Addr blk_addr
= blockAlign(pkt
->getAddr());
1936 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
1938 // Inform request(Prefetch, CleanEvict or Writeback) from below of
1939 // MSHR hit, set setBlockCached.
1940 if (mshr
&& pkt
->mustCheckAbove()) {
1941 DPRINTF(Cache
, "Setting block cached for %s from"
1942 "lower cache on mshr hit %#x\n",
1943 pkt
->cmdString(), pkt
->getAddr());
1944 pkt
->setBlockCached();
1948 // Let the MSHR itself track the snoop and decide whether we want
1949 // to go ahead and do the regular cache snoop
1950 if (mshr
&& mshr
->handleSnoop(pkt
, order
++)) {
1951 DPRINTF(Cache
, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
1952 "mshrs: %s\n", blk_addr
, is_secure
? "s" : "ns",
1955 if (mshr
->getNumTargets() > numTarget
)
1956 warn("allocating bonus target for snoop"); //handle later
1960 //We also need to check the writeback buffers and handle those
1961 std::vector
<MSHR
*> writebacks
;
1962 if (writeBuffer
.findMatches(blk_addr
, is_secure
, writebacks
)) {
1963 DPRINTF(Cache
, "Snoop hit in writeback to addr %#llx (%s)\n",
1964 pkt
->getAddr(), is_secure
? "s" : "ns");
1966 // Look through writebacks for any cachable writes.
1967 // We should only ever find a single match
1968 assert(writebacks
.size() == 1);
1969 MSHR
*wb_entry
= writebacks
[0];
1970 // Expect to see only Writebacks and/or CleanEvicts here, both of
1971 // which should not be generated for uncacheable data.
1972 assert(!wb_entry
->isUncacheable());
1973 // There should only be a single request responsible for generating
1974 // Writebacks/CleanEvicts.
1975 assert(wb_entry
->getNumTargets() == 1);
1976 PacketPtr wb_pkt
= wb_entry
->getTarget()->pkt
;
1977 assert(wb_pkt
->evictingBlock());
1979 if (pkt
->evictingBlock()) {
1980 // if the block is found in the write queue, set the BLOCK_CACHED
1981 // flag for Writeback/CleanEvict snoop. On return the snoop will
1982 // propagate the BLOCK_CACHED flag in Writeback packets and prevent
1983 // any CleanEvicts from travelling down the memory hierarchy.
1984 pkt
->setBlockCached();
1985 DPRINTF(Cache
, "Squashing %s from lower cache on writequeue hit"
1986 " %#x\n", pkt
->cmdString(), pkt
->getAddr());
1990 if (wb_pkt
->cmd
== MemCmd::Writeback
) {
1991 assert(!pkt
->memInhibitAsserted());
1992 pkt
->assertMemInhibit();
1993 if (!pkt
->needsExclusive()) {
1994 pkt
->assertShared();
1995 // the writeback is no longer passing exclusivity (the
1996 // receiving cache should consider the block owned
1997 // rather than modified)
1998 wb_pkt
->assertShared();
2000 // if we're not asserting the shared line, we need to
2001 // invalidate our copy. we'll do that below as long as
2002 // the packet's invalidate flag is set...
2003 assert(pkt
->isInvalidate());
2005 doTimingSupplyResponse(pkt
, wb_pkt
->getConstPtr
<uint8_t>(),
2008 assert(wb_pkt
->cmd
== MemCmd::CleanEvict
);
2009 // The cache technically holds the block until the
2010 // corresponding CleanEvict message reaches the crossbar
2011 // below. Therefore when a snoop encounters a CleanEvict
2012 // message we must set assertShared (just like when it
2013 // encounters a Writeback) to avoid the snoop filter
2014 // prematurely clearing the holder bit in the crossbar
2016 if (!pkt
->needsExclusive())
2017 pkt
->assertShared();
2019 assert(pkt
->isInvalidate());
2022 if (pkt
->isInvalidate()) {
2023 // Invalidation trumps our writeback... discard here
2024 // Note: markInService will remove entry from writeback buffer.
2025 markInService(wb_entry
, false);
2030 // If this was a shared writeback, there may still be
2031 // other shared copies above that require invalidation.
2032 // We could be more selective and return here if the
2033 // request is non-exclusive or if the writeback is
2035 handleSnoop(pkt
, blk
, true, false, false);
2039 Cache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt
)
2041 // Express snoop responses from master to slave, e.g., from L1 to L2
2042 cache
->recvTimingSnoopResp(pkt
);
2047 Cache::recvAtomicSnoop(PacketPtr pkt
)
2049 // Snoops shouldn't happen when bypassing caches
2050 assert(!system
->bypassCaches());
2052 // no need to snoop writebacks or requests that are not in range. In
2053 // atomic we have no Writebacks/CleanEvicts queued and no prefetches,
2054 // hence there is no need to snoop upwards and determine if they are
2056 if (pkt
->evictingBlock() || !inRange(pkt
->getAddr())) {
2060 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
2061 handleSnoop(pkt
, blk
, false, false, false);
2062 // We consider forwardLatency here because a snoop occurs in atomic mode
2063 return forwardLatency
* clockPeriod();
2068 Cache::getNextMSHR()
2070 // Check both MSHR queue and write buffer for potential requests,
2071 // note that null does not mean there is no request, it could
2072 // simply be that it is not ready
2073 MSHR
*miss_mshr
= mshrQueue
.getNextMSHR();
2074 MSHR
*write_mshr
= writeBuffer
.getNextMSHR();
2076 // If we got a write buffer request ready, first priority is a
2077 // full write buffer, otherwhise we favour the miss requests
2079 ((writeBuffer
.isFull() && writeBuffer
.inServiceEntries
== 0) ||
2081 // need to search MSHR queue for conflicting earlier miss.
2082 MSHR
*conflict_mshr
=
2083 mshrQueue
.findPending(write_mshr
->blkAddr
,
2084 write_mshr
->isSecure
);
2086 if (conflict_mshr
&& conflict_mshr
->order
< write_mshr
->order
) {
2087 // Service misses in order until conflict is cleared.
2088 return conflict_mshr
;
2090 // @todo Note that we ignore the ready time of the conflict here
2093 // No conflicts; issue write
2095 } else if (miss_mshr
) {
2096 // need to check for conflicting earlier writeback
2097 MSHR
*conflict_mshr
=
2098 writeBuffer
.findPending(miss_mshr
->blkAddr
,
2099 miss_mshr
->isSecure
);
2100 if (conflict_mshr
) {
2101 // not sure why we don't check order here... it was in the
2102 // original code but commented out.
2104 // The only way this happens is if we are
2105 // doing a write and we didn't have permissions
2106 // then subsequently saw a writeback (owned got evicted)
2107 // We need to make sure to perform the writeback first
2108 // To preserve the dirty data, then we can issue the write
2110 // should we return write_mshr here instead? I.e. do we
2111 // have to flush writes in order? I don't think so... not
2112 // for Alpha anyway. Maybe for x86?
2113 return conflict_mshr
;
2115 // @todo Note that we ignore the ready time of the conflict here
2118 // No conflicts; issue read
2122 // fall through... no pending requests. Try a prefetch.
2123 assert(!miss_mshr
&& !write_mshr
);
2124 if (prefetcher
&& mshrQueue
.canPrefetch()) {
2125 // If we have a miss queue slot, we can try a prefetch
2126 PacketPtr pkt
= prefetcher
->getPacket();
2128 Addr pf_addr
= blockAlign(pkt
->getAddr());
2129 if (!tags
->findBlock(pf_addr
, pkt
->isSecure()) &&
2130 !mshrQueue
.findMatch(pf_addr
, pkt
->isSecure()) &&
2131 !writeBuffer
.findMatch(pf_addr
, pkt
->isSecure())) {
2132 // Update statistic on number of prefetches issued
2133 // (hwpf_mshr_misses)
2134 assert(pkt
->req
->masterId() < system
->maxMasters());
2135 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
2137 // allocate an MSHR and return it, note
2138 // that we send the packet straight away, so do not
2139 // schedule the send
2140 return allocateMissBuffer(pkt
, curTick(), false);
2142 // free the request and packet
2153 Cache::isCachedAbove(const PacketPtr pkt
) const
2157 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
2158 // Writeback snoops into upper level caches to check for copies of the
2159 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
2160 // packet, the cache can inform the crossbar below of presence or absence
2163 Packet
snoop_pkt(pkt
, true, false);
2164 snoop_pkt
.setExpressSnoop();
2165 // Assert that packet is either Writeback or CleanEvict and not a prefetch
2166 // request because prefetch requests need an MSHR and may generate a snoop
2168 assert(pkt
->evictingBlock());
2169 snoop_pkt
.senderState
= NULL
;
2170 cpuSidePort
->sendTimingSnoopReq(&snoop_pkt
);
2171 // Writeback/CleanEvict snoops do not generate a separate snoop response.
2172 assert(!(snoop_pkt
.memInhibitAsserted()));
2173 return snoop_pkt
.isBlockCached();
2177 Cache::getTimingPacket()
2179 MSHR
*mshr
= getNextMSHR();
2185 // use request from 1st target
2186 PacketPtr tgt_pkt
= mshr
->getTarget()->pkt
;
2187 PacketPtr pkt
= NULL
;
2189 DPRINTF(CachePort
, "%s %s for addr %#llx size %d\n", __func__
,
2190 tgt_pkt
->cmdString(), tgt_pkt
->getAddr(), tgt_pkt
->getSize());
2192 CacheBlk
*blk
= tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
);
2194 if (tgt_pkt
->cmd
== MemCmd::HardPFReq
&& forwardSnoops
) {
2195 // We need to check the caches above us to verify that
2196 // they don't have a copy of this block in the dirty state
2197 // at the moment. Without this check we could get a stale
2198 // copy from memory that might get used in place of the
2200 Packet
snoop_pkt(tgt_pkt
, true, false);
2201 snoop_pkt
.setExpressSnoop();
2202 snoop_pkt
.senderState
= mshr
;
2203 cpuSidePort
->sendTimingSnoopReq(&snoop_pkt
);
2205 // Check to see if the prefetch was squashed by an upper cache (to
2206 // prevent us from grabbing the line) or if a Check to see if a
2207 // writeback arrived between the time the prefetch was placed in
2208 // the MSHRs and when it was selected to be sent or if the
2209 // prefetch was squashed by an upper cache.
2211 // It is important to check memInhibitAsserted before
2212 // prefetchSquashed. If another cache has asserted MEM_INGIBIT, it
2213 // will be sending a response which will arrive at the MSHR
2214 // allocated ofr this request. Checking the prefetchSquash first
2215 // may result in the MSHR being prematurely deallocated.
2217 if (snoop_pkt
.memInhibitAsserted()) {
2218 // If we are getting a non-shared response it is dirty
2219 bool pending_dirty_resp
= !snoop_pkt
.sharedAsserted();
2220 markInService(mshr
, pending_dirty_resp
);
2221 DPRINTF(Cache
, "Upward snoop of prefetch for addr"
2223 tgt_pkt
->getAddr(), tgt_pkt
->isSecure()? "s": "ns");
2227 if (snoop_pkt
.isBlockCached() || blk
!= NULL
) {
2228 DPRINTF(Cache
, "Block present, prefetch squashed by cache. "
2229 "Deallocating mshr target %#x.\n",
2232 // Deallocate the mshr target
2233 if (tgt_pkt
->cmd
!= MemCmd::Writeback
) {
2234 if (mshr
->queue
->forceDeallocateTarget(mshr
)) {
2235 // Clear block if this deallocation resulted freed an
2236 // mshr when all had previously been utilized
2237 clearBlocked((BlockedCause
)(mshr
->queue
->index
));
2241 // If this is a Writeback, and the snoops indicate that the blk
2242 // is cached above, set the BLOCK_CACHED flag in the Writeback
2243 // packet, so that it does not reset the bits corresponding to
2244 // this block in the snoop filter below.
2245 tgt_pkt
->setBlockCached();
2250 if (mshr
->isForwardNoResponse()) {
2251 // no response expected, just forward packet as it is
2252 assert(tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
) == NULL
);
2255 pkt
= getBusPacket(tgt_pkt
, blk
, mshr
->needsExclusive());
2257 mshr
->isForward
= (pkt
== NULL
);
2259 if (mshr
->isForward
) {
2260 // not a cache block request, but a response is expected
2261 // make copy of current packet to forward, keep current
2262 // copy for response handling
2263 pkt
= new Packet(tgt_pkt
, false, true);
2264 if (pkt
->isWrite()) {
2265 pkt
->setData(tgt_pkt
->getConstPtr
<uint8_t>());
2270 assert(pkt
!= NULL
);
2271 pkt
->senderState
= mshr
;
2277 Cache::nextMSHRReadyTime() const
2279 Tick nextReady
= std::min(mshrQueue
.nextMSHRReadyTime(),
2280 writeBuffer
.nextMSHRReadyTime());
2282 // Don't signal prefetch ready time if no MSHRs available
2283 // Will signal once enoguh MSHRs are deallocated
2284 if (prefetcher
&& mshrQueue
.canPrefetch()) {
2285 nextReady
= std::min(nextReady
,
2286 prefetcher
->nextPrefetchReadyTime());
2293 Cache::serialize(CheckpointOut
&cp
) const
2295 bool dirty(isDirty());
2298 warn("*** The cache still contains dirty data. ***\n");
2299 warn(" Make sure to drain the system using the correct flags.\n");
2300 warn(" This checkpoint will not restore correctly and dirty data in "
2301 "the cache will be lost!\n");
2304 // Since we don't checkpoint the data in the cache, any dirty data
2305 // will be lost when restoring from a checkpoint of a system that
2306 // wasn't drained properly. Flag the checkpoint as invalid if the
2307 // cache contains dirty data.
2308 bool bad_checkpoint(dirty
);
2309 SERIALIZE_SCALAR(bad_checkpoint
);
2313 Cache::unserialize(CheckpointIn
&cp
)
2315 bool bad_checkpoint
;
2316 UNSERIALIZE_SCALAR(bad_checkpoint
);
2317 if (bad_checkpoint
) {
2318 fatal("Restoring from checkpoints with dirty caches is not supported "
2319 "in the classic memory system. Please remove any caches or "
2320 " drain them properly before taking checkpoints.\n");
2331 Cache::CpuSidePort::getAddrRanges() const
2333 return cache
->getAddrRanges();
2337 Cache::CpuSidePort::recvTimingReq(PacketPtr pkt
)
2339 assert(!cache
->system
->bypassCaches());
2341 bool success
= false;
2343 // always let inhibited requests through, even if blocked,
2344 // ultimately we should check if this is an express snoop, but at
2345 // the moment that flag is only set in the cache itself
2346 if (pkt
->memInhibitAsserted()) {
2347 // do not change the current retry state
2348 bool M5_VAR_USED bypass_success
= cache
->recvTimingReq(pkt
);
2349 assert(bypass_success
);
2351 } else if (blocked
|| mustSendRetry
) {
2352 // either already committed to send a retry, or blocked
2355 // pass it on to the cache, and let the cache decide if we
2356 // have to retry or not
2357 success
= cache
->recvTimingReq(pkt
);
2360 // remember if we have to retry
2361 mustSendRetry
= !success
;
2366 Cache::CpuSidePort::recvAtomic(PacketPtr pkt
)
2368 return cache
->recvAtomic(pkt
);
2372 Cache::CpuSidePort::recvFunctional(PacketPtr pkt
)
2374 // functional request
2375 cache
->functionalAccess(pkt
, true);
2379 CpuSidePort::CpuSidePort(const std::string
&_name
, Cache
*_cache
,
2380 const std::string
&_label
)
2381 : BaseCache::CacheSlavePort(_name
, _cache
, _label
), cache(_cache
)
2386 CacheParams::create()
2390 return new Cache(this);
2399 Cache::MemSidePort::recvTimingResp(PacketPtr pkt
)
2401 cache
->recvTimingResp(pkt
);
2405 // Express snooping requests to memside port
2407 Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt
)
2409 // handle snooping requests
2410 cache
->recvTimingSnoopReq(pkt
);
2414 Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt
)
2416 return cache
->recvAtomicSnoop(pkt
);
2420 Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt
)
2422 // functional snoop (note that in contrast to atomic we don't have
2423 // a specific functionalSnoop method, as they have the same
2424 // behaviour regardless)
2425 cache
->functionalAccess(pkt
, false);
2429 Cache::CacheReqPacketQueue::sendDeferredPacket()
2432 assert(!waitingOnRetry
);
2434 // there should never be any deferred request packets in the
2435 // queue, instead we resly on the cache to provide the packets
2436 // from the MSHR queue or write queue
2437 assert(deferredPacketReadyTime() == MaxTick
);
2439 // check for request packets (requests & writebacks)
2440 PacketPtr pkt
= cache
.getTimingPacket();
2442 // can happen if e.g. we attempt a writeback and fail, but
2443 // before the retry, the writeback is eliminated because
2444 // we snoop another cache's ReadEx.
2446 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->senderState
);
2447 // in most cases getTimingPacket allocates a new packet, and
2448 // we must delete it unless it is successfully sent
2449 bool delete_pkt
= !mshr
->isForwardNoResponse();
2451 // let our snoop responses go first if there are responses to
2452 // the same addresses we are about to writeback, note that
2453 // this creates a dependency between requests and snoop
2454 // responses, but that should not be a problem since there is
2455 // a chain already and the key is that the snoop responses can
2456 // sink unconditionally
2457 if (snoopRespQueue
.hasAddr(pkt
->getAddr())) {
2458 DPRINTF(CachePort
, "Waiting for snoop response to be sent\n");
2459 Tick when
= snoopRespQueue
.deferredPacketReadyTime();
2460 schedSendEvent(when
);
2469 waitingOnRetry
= !masterPort
.sendTimingReq(pkt
);
2471 if (waitingOnRetry
) {
2472 DPRINTF(CachePort
, "now waiting on a retry\n");
2474 // we are awaiting a retry, but we
2475 // delete the packet and will be creating a new packet
2476 // when we get the opportunity
2479 // note that we have now masked any requestBus and
2480 // schedSendEvent (we will wait for a retry before
2481 // doing anything), and this is so even if we do not
2482 // care about this packet and might override it before
2485 // As part of the call to sendTimingReq the packet is
2486 // forwarded to all neighbouring caches (and any
2487 // caches above them) as a snoop. The packet is also
2488 // sent to any potential cache below as the
2489 // interconnect is not allowed to buffer the
2490 // packet. Thus at this point we know if any of the
2491 // neighbouring, or the downstream cache is
2492 // responding, and if so, if it is with a dirty line
2494 bool pending_dirty_resp
= !pkt
->sharedAsserted() &&
2495 pkt
->memInhibitAsserted();
2497 cache
.markInService(mshr
, pending_dirty_resp
);
2501 // if we succeeded and are not waiting for a retry, schedule the
2502 // next send considering when the next MSHR is ready, note that
2503 // snoop responses have their own packet queue and thus schedule
2505 if (!waitingOnRetry
) {
2506 schedSendEvent(cache
.nextMSHRReadyTime());
2511 MemSidePort::MemSidePort(const std::string
&_name
, Cache
*_cache
,
2512 const std::string
&_label
)
2513 : BaseCache::CacheMasterPort(_name
, _cache
, _reqQueue
, _snoopRespQueue
),
2514 _reqQueue(*_cache
, *this, _snoopRespQueue
, _label
),
2515 _snoopRespQueue(*_cache
, *this, _label
), cache(_cache
)