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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
52 #ifndef __MEM_CACHE_CACHE_HH__
53 #define __MEM_CACHE_CACHE_HH__
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "mem/cache/base.hh"
57 #include "mem/cache/blk.hh"
58 #include "mem/cache/mshr.hh"
59 #include "mem/cache/tags/base.hh"
60 #include "sim/eventq.hh"
66 * A template-policy based cache. The behavior of the cache can be altered by
67 * supplying different template policies. TagStore handles all tag and data
68 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
70 class Cache : public BaseCache
74 /** A typedef for a list of CacheBlk pointers. */
75 typedef std::list<CacheBlk*> BlkList;
80 * The CPU-side port extends the base cache slave port with access
81 * functions for functional, atomic and timing requests.
83 class CpuSidePort : public CacheSlavePort
87 // a pointer to our specific cache implementation
92 virtual bool recvTimingSnoopResp(PacketPtr pkt);
94 virtual bool recvTimingReq(PacketPtr pkt);
96 virtual Tick recvAtomic(PacketPtr pkt);
98 virtual void recvFunctional(PacketPtr pkt);
100 virtual AddrRangeList getAddrRanges() const;
104 CpuSidePort(const std::string &_name, Cache *_cache,
105 const std::string &_label);
110 * Override the default behaviour of sendDeferredPacket to enable
111 * the memory-side cache port to also send requests based on the
112 * current MSHR status. This queue has a pointer to our specific
113 * cache implementation and is used by the MemSidePort.
115 class CacheReqPacketQueue : public ReqPacketQueue
121 SnoopRespPacketQueue &snoopRespQueue;
125 CacheReqPacketQueue(Cache &cache, MasterPort &port,
126 SnoopRespPacketQueue &snoop_resp_queue,
127 const std::string &label) :
128 ReqPacketQueue(cache, port, label), cache(cache),
129 snoopRespQueue(snoop_resp_queue) { }
132 * Override the normal sendDeferredPacket and do not only
133 * consider the transmit list (used for responses), but also
136 virtual void sendDeferredPacket();
141 * The memory-side port extends the base cache master port with
142 * access functions for functional, atomic and timing snoops.
144 class MemSidePort : public CacheMasterPort
148 /** The cache-specific queue. */
149 CacheReqPacketQueue _reqQueue;
151 SnoopRespPacketQueue _snoopRespQueue;
153 // a pointer to our specific cache implementation
158 virtual void recvTimingSnoopReq(PacketPtr pkt);
160 virtual bool recvTimingResp(PacketPtr pkt);
162 virtual Tick recvAtomicSnoop(PacketPtr pkt);
164 virtual void recvFunctionalSnoop(PacketPtr pkt);
168 MemSidePort(const std::string &_name, Cache *_cache,
169 const std::string &_label);
172 /** Tag and data Storage */
176 BasePrefetcher *prefetcher;
178 /** Temporary cache block for occasional transitory use */
182 * This cache should allocate a block on a line-sized write miss.
184 const bool doFastWrites;
187 * Turn line-sized writes into WriteInvalidate transactions.
189 void promoteWholeLineWrites(PacketPtr pkt);
192 * Notify the prefetcher on every access, not just misses.
194 const bool prefetchOnAccess;
197 * @todo this is a temporary workaround until the 4-phase code is committed.
198 * upstream caches need this packet until true is returned, so hold it for
199 * deletion until a subsequent call
201 std::vector<PacketPtr> pendingDelete;
204 * Does all the processing necessary to perform the provided request.
205 * @param pkt The memory request to perform.
206 * @param blk The cache block to be updated.
207 * @param lat The latency of the access.
208 * @param writebacks List for any writebacks that need to be performed.
209 * @return Boolean indicating whether the request was satisfied.
211 bool access(PacketPtr pkt, CacheBlk *&blk,
212 Cycles &lat, PacketList &writebacks);
215 *Handle doing the Compare and Swap function for SPARC.
217 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
220 * Find a block frame for new block at address addr targeting the
221 * given security space, assuming that the block is not currently
222 * in the cache. Append writebacks if any to provided packet
223 * list. Return free block frame. May return NULL if there are
224 * no replaceable blocks at the moment.
226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
229 * Populates a cache block and handles all outstanding requests for the
230 * satisfied fill request. This version takes two memory requests. One
231 * contains the fill data, the other is an optional target to satisfy.
232 * @param pkt The memory request with the fill data.
233 * @param blk The cache block if it already exists.
234 * @param writebacks List for any writebacks that need to be performed.
235 * @return Pointer to the new cache block.
237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
238 PacketList &writebacks);
242 * Performs the access specified by the request.
243 * @param pkt The request to perform.
244 * @return The result of the access.
246 bool recvTimingReq(PacketPtr pkt);
249 * Insert writebacks into the write buffer
251 void doWritebacks(PacketList& writebacks, Tick forward_time);
254 * Handles a response (cache line fill/write ack) from the bus.
255 * @param pkt The response packet
257 void recvTimingResp(PacketPtr pkt);
260 * Snoops bus transactions to maintain coherence.
261 * @param pkt The current bus transaction.
263 void recvTimingSnoopReq(PacketPtr pkt);
266 * Handle a snoop response.
267 * @param pkt Snoop response packet
269 void recvTimingSnoopResp(PacketPtr pkt);
272 * Performs the access specified by the request.
273 * @param pkt The request to perform.
274 * @return The number of ticks required for the access.
276 Tick recvAtomic(PacketPtr pkt);
279 * Snoop for the provided request in the cache and return the estimated
281 * @param pkt The memory request to snoop
282 * @return The number of ticks required for the snoop.
284 Tick recvAtomicSnoop(PacketPtr pkt);
287 * Performs the access specified by the request.
288 * @param pkt The request to perform.
289 * @param fromCpuSide from the CPU side port or the memory side port
291 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
293 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
294 bool deferred_response = false,
295 bool pending_downgrade = false);
296 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
298 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
299 bool already_copied, bool pending_inval);
302 * Sets the blk to the new state.
303 * @param blk The cache block being snooped.
304 * @param new_state The new coherence state for the block.
306 void handleSnoop(PacketPtr ptk, CacheBlk *blk,
307 bool is_timing, bool is_deferred, bool pending_inval);
310 * Create a writeback request for the given block.
311 * @param blk The block to writeback.
312 * @return The writeback request for the block.
314 PacketPtr writebackBlk(CacheBlk *blk);
317 * Create a CleanEvict request for the given block.
318 * @param blk The block to evict.
319 * @return The CleanEvict request for the block.
321 PacketPtr cleanEvictBlk(CacheBlk *blk);
325 void memInvalidate();
326 bool isDirty() const;
329 * Cache block visitor that writes back dirty cache blocks using
332 * \return Always returns true.
334 bool writebackVisitor(CacheBlk &blk);
336 * Cache block visitor that invalidates all blocks in the cache.
338 * @warn Dirty cache lines will not be written back to memory.
340 * \return Always returns true.
342 bool invalidateVisitor(CacheBlk &blk);
345 * Squash all requests associated with specified thread.
346 * intended for use by I-cache.
347 * @param threadNum The thread to squash.
349 void squash(int threadNum);
352 * Generate an appropriate downstream bus request packet for the
354 * @param cpu_pkt The upstream request that needs to be satisfied.
355 * @param blk The block currently in the cache corresponding to
356 * cpu_pkt (NULL if none).
357 * @param needsExclusive Indicates that an exclusive copy is required
358 * even if the request in cpu_pkt doesn't indicate that.
359 * @return A new Packet containing the request, or NULL if the
360 * current request in cpu_pkt should just be forwarded on.
362 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
363 bool needsExclusive) const;
366 * Return the next MSHR to service, either a pending miss from the
367 * mshrQueue, a buffered write from the write buffer, or something
368 * from the prefetcher. This function is responsible for
369 * prioritizing among those sources on the fly.
374 * Send up a snoop request and find cached copies. If cached copies are
375 * found, set the BLOCK_CACHED flag in pkt.
377 bool isCachedAbove(const PacketPtr pkt) const;
380 * Selects an outstanding request to service. Called when the
381 * cache gets granted the downstream bus in timing mode.
382 * @return The request to service, NULL if none found.
384 PacketPtr getTimingPacket();
387 * Marks a request as in service (sent on the bus). This can have
388 * side effect since storage for no response commands is
389 * deallocated once they are successfully sent. Also remember if
390 * we are expecting a dirty response from another cache,
391 * effectively making this MSHR the ordering point.
393 void markInService(MSHR *mshr, bool pending_dirty_resp);
396 * Return whether there are any outstanding misses.
398 bool outstandingMisses() const
400 return mshrQueue.allocated != 0;
403 CacheBlk *findBlock(Addr addr, bool is_secure) const {
404 return tags->findBlock(addr, is_secure);
407 bool inCache(Addr addr, bool is_secure) const {
408 return (tags->findBlock(addr, is_secure) != 0);
411 bool inMissQueue(Addr addr, bool is_secure) const {
412 return (mshrQueue.findMatch(addr, is_secure) != 0);
416 * Find next request ready time from among possible sources.
418 Tick nextMSHRReadyTime() const;
421 /** Instantiates a basic cache object. */
422 Cache(const Params *p);
424 /** Non-default destructor is needed to deallocate memory. */
429 /** serialize the state of the caches
430 * We currently don't support checkpointing cache state, so this panics.
432 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
433 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
437 * Wrap a method and present it as a cache block visitor.
439 * For example the forEachBlk method in the tag arrays expects a
440 * callable object/function as their parameter. This class wraps a
441 * method in an object and presents callable object that adheres to
442 * the cache block visitor protocol.
444 class CacheBlkVisitorWrapper : public CacheBlkVisitor
447 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
449 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
450 : cache(_cache), visitor(_visitor) {}
452 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
453 return (cache.*visitor)(blk);
462 * Cache block visitor that determines if there are dirty blocks in a
465 * Use with the forEachBlk method in the tag array to determine if the
466 * array contains dirty blocks.
468 class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
471 CacheBlkIsDirtyVisitor()
474 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
484 * Does the array contain a dirty line?
486 * \return true if yes, false otherwise.
488 bool isDirty() const { return _isDirty; };
494 #endif // __MEM_CACHE_CACHE_HH__