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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "mem/cache/base.hh"
57 #include "mem/cache/blk.hh"
58 #include "mem/cache/mshr.hh"
59 #include "sim/eventq.hh"
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore.
69 template <class TagStore>
70 class Cache : public BaseCache
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
84 class CpuSidePort : public CacheSlavePort
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
93 virtual bool recvTiming(PacketPtr pkt);
95 virtual Tick recvAtomic(PacketPtr pkt);
97 virtual void recvFunctional(PacketPtr pkt);
99 virtual unsigned deviceBlockSize() const
100 { return cache->getBlockSize(); }
102 virtual AddrRangeList getAddrRanges();
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
112 * The memory-side port extends the base cache master port with
113 * access functions for functional, atomic and timing snoops.
115 class MemSidePort : public CacheMasterPort
119 // a pointer to our specific cache implementation
120 Cache<TagStore> *cache;
124 virtual bool recvTiming(PacketPtr pkt);
126 virtual Tick recvAtomic(PacketPtr pkt);
128 virtual void recvFunctional(PacketPtr pkt);
130 virtual unsigned deviceBlockSize() const
131 { return cache->getBlockSize(); }
135 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
136 const std::string &_label);
139 * Overload sendDeferredPacket of SimpleTimingPort.
141 virtual void sendDeferredPacket();
144 /** Tag and data Storage */
148 BasePrefetcher *prefetcher;
150 /** Temporary cache block for occasional transitory use */
154 * This cache should allocate a block on a line-sized write miss.
156 const bool doFastWrites;
159 * Notify the prefetcher on every access, not just misses.
161 const bool prefetchOnAccess;
164 * Does all the processing necessary to perform the provided request.
165 * @param pkt The memory request to perform.
166 * @param lat The latency of the access.
167 * @param writebacks List for any writebacks that need to be performed.
168 * @param update True if the replacement data should be updated.
169 * @return Boolean indicating whether the request was satisfied.
171 bool access(PacketPtr pkt, BlkType *&blk,
172 int &lat, PacketList &writebacks);
175 *Handle doing the Compare and Swap function for SPARC.
177 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
180 * Find a block frame for new block at address addr, assuming that
181 * the block is not currently in the cache. Append writebacks if
182 * any to provided packet list. Return free block frame. May
183 * return NULL if there are no replaceable blocks at the moment.
185 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
188 * Populates a cache block and handles all outstanding requests for the
189 * satisfied fill request. This version takes two memory requests. One
190 * contains the fill data, the other is an optional target to satisfy.
191 * @param pkt The memory request with the fill data.
192 * @param blk The cache block if it already exists.
193 * @param writebacks List for any writebacks that need to be performed.
194 * @return Pointer to the new cache block.
196 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
197 PacketList &writebacks);
199 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
200 bool deferred_response = false,
201 bool pending_downgrade = false);
202 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
204 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
205 bool already_copied, bool pending_inval);
208 * Sets the blk to the new state.
209 * @param blk The cache block being snooped.
210 * @param new_state The new coherence state for the block.
212 void handleSnoop(PacketPtr ptk, BlkType *blk,
213 bool is_timing, bool is_deferred, bool pending_inval);
216 * Create a writeback request for the given block.
217 * @param blk The block to writeback.
218 * @return The writeback request for the block.
220 PacketPtr writebackBlk(BlkType *blk);
223 /** Instantiates a basic cache object. */
224 Cache(const Params *p, TagStore *tags);
226 virtual Port *getPort(const std::string &if_name, int idx = -1);
231 * Performs the access specified by the request.
232 * @param pkt The request to perform.
233 * @return The result of the access.
235 bool timingAccess(PacketPtr pkt);
238 * Performs the access specified by the request.
239 * @param pkt The request to perform.
240 * @return The result of the access.
242 Tick atomicAccess(PacketPtr pkt);
245 * Performs the access specified by the request.
246 * @param pkt The request to perform.
247 * @param fromCpuSide from the CPU side port or the memory side port
249 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
252 * Handles a response (cache line fill/write ack) from the bus.
253 * @param pkt The request being responded to.
255 void handleResponse(PacketPtr pkt);
258 * Snoops bus transactions to maintain coherence.
259 * @param pkt The current bus transaction.
261 void snoopTiming(PacketPtr pkt);
264 * Snoop for the provided request in the cache and return the estimated
265 * time of completion.
266 * @param pkt The memory request to snoop
267 * @return The estimated completion time.
269 Tick snoopAtomic(PacketPtr pkt);
272 * Squash all requests associated with specified thread.
273 * intended for use by I-cache.
274 * @param threadNum The thread to squash.
276 void squash(int threadNum);
279 * Generate an appropriate downstream bus request packet for the
281 * @param cpu_pkt The upstream request that needs to be satisfied.
282 * @param blk The block currently in the cache corresponding to
283 * cpu_pkt (NULL if none).
284 * @param needsExclusive Indicates that an exclusive copy is required
285 * even if the request in cpu_pkt doesn't indicate that.
286 * @return A new Packet containing the request, or NULL if the
287 * current request in cpu_pkt should just be forwarded on.
289 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
290 bool needsExclusive);
293 * Return the next MSHR to service, either a pending miss from the
294 * mshrQueue, a buffered write from the write buffer, or something
295 * from the prefetcher. This function is responsible for
296 * prioritizing among those sources on the fly.
301 * Selects an outstanding request to service. Called when the
302 * cache gets granted the downstream bus in timing mode.
303 * @return The request to service, NULL if none found.
305 PacketPtr getTimingPacket();
308 * Marks a request as in service (sent on the bus). This can have side
309 * effect since storage for no response commands is deallocated once they
310 * are successfully sent.
311 * @param pkt The request that was sent on the bus.
313 void markInService(MSHR *mshr, PacketPtr pkt = 0);
316 * Perform the given writeback request.
317 * @param pkt The writeback request.
319 void doWriteback(PacketPtr pkt);
322 * Return whether there are any outstanding misses.
324 bool outstandingMisses() const
326 return mshrQueue.allocated != 0;
329 CacheBlk *findBlock(Addr addr) {
330 return tags->findBlock(addr);
333 bool inCache(Addr addr) {
334 return (tags->findBlock(addr) != 0);
337 bool inMissQueue(Addr addr) {
338 return (mshrQueue.findMatch(addr) != 0);
342 * Find next request ready time from among possible sources.
344 Tick nextMSHRReadyTime();
347 #endif // __CACHE_HH__