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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "mem/cache/base.hh"
57 #include "mem/cache/blk.hh"
58 #include "mem/cache/mshr.hh"
59 #include "sim/eventq.hh"
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
69 template <class TagStore>
70 class Cache : public BaseCache
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
84 class CpuSidePort : public CacheSlavePort
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
93 virtual bool recvTimingSnoopResp(PacketPtr pkt);
95 virtual bool recvTimingReq(PacketPtr pkt);
97 virtual Tick recvAtomic(PacketPtr pkt);
99 virtual void recvFunctional(PacketPtr pkt);
101 virtual unsigned deviceBlockSize() const
102 { return cache->getBlockSize(); }
104 virtual AddrRangeList getAddrRanges() const;
108 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
109 const std::string &_label);
114 * Override the default behaviour of sendDeferredPacket to enable
115 * the memory-side cache port to also send requests based on the
116 * current MSHR status. This queue has a pointer to our specific
117 * cache implementation and is used by the MemSidePort.
119 class MemSidePacketQueue : public MasterPacketQueue
124 Cache<TagStore> &cache;
128 MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
129 const std::string &label) :
130 MasterPacketQueue(cache, port, label), cache(cache) { }
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
137 virtual void sendDeferredPacket();
142 * The memory-side port extends the base cache master port with
143 * access functions for functional, atomic and timing snoops.
145 class MemSidePort : public CacheMasterPort
149 /** The cache-specific queue. */
150 MemSidePacketQueue _queue;
152 // a pointer to our specific cache implementation
153 Cache<TagStore> *cache;
157 virtual void recvTimingSnoopReq(PacketPtr pkt);
159 virtual bool recvTimingResp(PacketPtr pkt);
161 virtual Tick recvAtomicSnoop(PacketPtr pkt);
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
165 virtual unsigned deviceBlockSize() const
166 { return cache->getBlockSize(); }
170 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
171 const std::string &_label);
174 /** Tag and data Storage */
178 BasePrefetcher *prefetcher;
180 /** Temporary cache block for occasional transitory use */
184 * This cache should allocate a block on a line-sized write miss.
186 const bool doFastWrites;
189 * Notify the prefetcher on every access, not just misses.
191 const bool prefetchOnAccess;
194 * @todo this is a temporary workaround until the 4-phase code is committed.
195 * upstream caches need this packet until true is returned, so hold it for
196 * deletion until a subsequent call
198 std::vector<PacketPtr> pendingDelete;
201 * Does all the processing necessary to perform the provided request.
202 * @param pkt The memory request to perform.
203 * @param lat The latency of the access.
204 * @param writebacks List for any writebacks that need to be performed.
205 * @param update True if the replacement data should be updated.
206 * @return Boolean indicating whether the request was satisfied.
208 bool access(PacketPtr pkt, BlkType *&blk,
209 int &lat, PacketList &writebacks);
212 *Handle doing the Compare and Swap function for SPARC.
214 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
217 * Find a block frame for new block at address addr, assuming that
218 * the block is not currently in the cache. Append writebacks if
219 * any to provided packet list. Return free block frame. May
220 * return NULL if there are no replaceable blocks at the moment.
222 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
225 * Populates a cache block and handles all outstanding requests for the
226 * satisfied fill request. This version takes two memory requests. One
227 * contains the fill data, the other is an optional target to satisfy.
228 * @param pkt The memory request with the fill data.
229 * @param blk The cache block if it already exists.
230 * @param writebacks List for any writebacks that need to be performed.
231 * @return Pointer to the new cache block.
233 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
234 PacketList &writebacks);
236 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
237 bool deferred_response = false,
238 bool pending_downgrade = false);
239 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
241 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
242 bool already_copied, bool pending_inval);
245 * Sets the blk to the new state.
246 * @param blk The cache block being snooped.
247 * @param new_state The new coherence state for the block.
249 void handleSnoop(PacketPtr ptk, BlkType *blk,
250 bool is_timing, bool is_deferred, bool pending_inval);
253 * Create a writeback request for the given block.
254 * @param blk The block to writeback.
255 * @return The writeback request for the block.
257 PacketPtr writebackBlk(BlkType *blk);
260 /** Instantiates a basic cache object. */
261 Cache(const Params *p, TagStore *tags);
266 * Performs the access specified by the request.
267 * @param pkt The request to perform.
268 * @return The result of the access.
270 bool timingAccess(PacketPtr pkt);
273 * Performs the access specified by the request.
274 * @param pkt The request to perform.
275 * @return The result of the access.
277 Tick atomicAccess(PacketPtr pkt);
280 * Performs the access specified by the request.
281 * @param pkt The request to perform.
282 * @param fromCpuSide from the CPU side port or the memory side port
284 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
287 * Handles a response (cache line fill/write ack) from the bus.
288 * @param pkt The request being responded to.
290 void handleResponse(PacketPtr pkt);
293 * Snoops bus transactions to maintain coherence.
294 * @param pkt The current bus transaction.
296 void snoopTiming(PacketPtr pkt);
299 * Snoop for the provided request in the cache and return the estimated
300 * time of completion.
301 * @param pkt The memory request to snoop
302 * @return The estimated completion time.
304 Tick snoopAtomic(PacketPtr pkt);
307 * Squash all requests associated with specified thread.
308 * intended for use by I-cache.
309 * @param threadNum The thread to squash.
311 void squash(int threadNum);
314 * Generate an appropriate downstream bus request packet for the
316 * @param cpu_pkt The upstream request that needs to be satisfied.
317 * @param blk The block currently in the cache corresponding to
318 * cpu_pkt (NULL if none).
319 * @param needsExclusive Indicates that an exclusive copy is required
320 * even if the request in cpu_pkt doesn't indicate that.
321 * @return A new Packet containing the request, or NULL if the
322 * current request in cpu_pkt should just be forwarded on.
324 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
325 bool needsExclusive);
328 * Return the next MSHR to service, either a pending miss from the
329 * mshrQueue, a buffered write from the write buffer, or something
330 * from the prefetcher. This function is responsible for
331 * prioritizing among those sources on the fly.
336 * Selects an outstanding request to service. Called when the
337 * cache gets granted the downstream bus in timing mode.
338 * @return The request to service, NULL if none found.
340 PacketPtr getTimingPacket();
343 * Marks a request as in service (sent on the bus). This can have side
344 * effect since storage for no response commands is deallocated once they
345 * are successfully sent.
346 * @param pkt The request that was sent on the bus.
348 void markInService(MSHR *mshr, PacketPtr pkt = 0);
351 * Return whether there are any outstanding misses.
353 bool outstandingMisses() const
355 return mshrQueue.allocated != 0;
358 CacheBlk *findBlock(Addr addr) {
359 return tags->findBlock(addr);
362 bool inCache(Addr addr) {
363 return (tags->findBlock(addr) != 0);
366 bool inMissQueue(Addr addr) {
367 return (mshrQueue.findMatch(addr) != 0);
371 * Find next request ready time from among possible sources.
373 Tick nextMSHRReadyTime();
375 /** serialize the state of the caches
376 * We currently don't support checkpointing cache state, so this panics.
378 virtual void serialize(std::ostream &os);
379 void unserialize(Checkpoint *cp, const std::string §ion);
382 #endif // __CACHE_HH__