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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "mem/cache/base.hh"
57 #include "mem/cache/blk.hh"
58 #include "mem/cache/mshr.hh"
59 #include "sim/eventq.hh"
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
69 template <class TagStore>
70 class Cache : public BaseCache
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
79 typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
82 * The CPU-side port extends the base cache slave port with access
83 * functions for functional, atomic and timing requests.
85 class CpuSidePort : public CacheSlavePort
89 // a pointer to our specific cache implementation
90 Cache<TagStore> *cache;
94 virtual bool recvTimingSnoopResp(PacketPtr pkt);
96 virtual bool recvTimingReq(PacketPtr pkt);
98 virtual Tick recvAtomic(PacketPtr pkt);
100 virtual void recvFunctional(PacketPtr pkt);
102 virtual AddrRangeList getAddrRanges() const;
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
112 * Override the default behaviour of sendDeferredPacket to enable
113 * the memory-side cache port to also send requests based on the
114 * current MSHR status. This queue has a pointer to our specific
115 * cache implementation and is used by the MemSidePort.
117 class MemSidePacketQueue : public MasterPacketQueue
122 Cache<TagStore> &cache;
126 MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
127 const std::string &label) :
128 MasterPacketQueue(cache, port, label), cache(cache) { }
131 * Override the normal sendDeferredPacket and do not only
132 * consider the transmit list (used for responses), but also
135 virtual void sendDeferredPacket();
140 * The memory-side port extends the base cache master port with
141 * access functions for functional, atomic and timing snoops.
143 class MemSidePort : public CacheMasterPort
147 /** The cache-specific queue. */
148 MemSidePacketQueue _queue;
150 // a pointer to our specific cache implementation
151 Cache<TagStore> *cache;
155 virtual void recvTimingSnoopReq(PacketPtr pkt);
157 virtual bool recvTimingResp(PacketPtr pkt);
159 virtual Tick recvAtomicSnoop(PacketPtr pkt);
161 virtual void recvFunctionalSnoop(PacketPtr pkt);
165 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
166 const std::string &_label);
169 /** Tag and data Storage */
173 BasePrefetcher *prefetcher;
175 /** Temporary cache block for occasional transitory use */
179 * This cache should allocate a block on a line-sized write miss.
181 const bool doFastWrites;
184 * Notify the prefetcher on every access, not just misses.
186 const bool prefetchOnAccess;
189 * @todo this is a temporary workaround until the 4-phase code is committed.
190 * upstream caches need this packet until true is returned, so hold it for
191 * deletion until a subsequent call
193 std::vector<PacketPtr> pendingDelete;
196 * Does all the processing necessary to perform the provided request.
197 * @param pkt The memory request to perform.
198 * @param blk The cache block to be updated.
199 * @param lat The latency of the access.
200 * @param writebacks List for any writebacks that need to be performed.
201 * @return Boolean indicating whether the request was satisfied.
203 bool access(PacketPtr pkt, BlkType *&blk,
204 Cycles &lat, PacketList &writebacks);
207 *Handle doing the Compare and Swap function for SPARC.
209 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
212 * Find a block frame for new block at address addr targeting the
213 * given security space, assuming that the block is not currently
214 * in the cache. Append writebacks if any to provided packet
215 * list. Return free block frame. May return NULL if there are
216 * no replaceable blocks at the moment.
218 BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
221 * Populates a cache block and handles all outstanding requests for the
222 * satisfied fill request. This version takes two memory requests. One
223 * contains the fill data, the other is an optional target to satisfy.
224 * @param pkt The memory request with the fill data.
225 * @param blk The cache block if it already exists.
226 * @param writebacks List for any writebacks that need to be performed.
227 * @return Pointer to the new cache block.
229 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
230 PacketList &writebacks);
234 * Performs the access specified by the request.
235 * @param pkt The request to perform.
236 * @return The result of the access.
238 bool recvTimingReq(PacketPtr pkt);
241 * Handles a response (cache line fill/write ack) from the bus.
242 * @param pkt The response packet
244 void recvTimingResp(PacketPtr pkt);
247 * Snoops bus transactions to maintain coherence.
248 * @param pkt The current bus transaction.
250 void recvTimingSnoopReq(PacketPtr pkt);
253 * Handle a snoop response.
254 * @param pkt Snoop response packet
256 void recvTimingSnoopResp(PacketPtr pkt);
259 * Performs the access specified by the request.
260 * @param pkt The request to perform.
261 * @return The number of ticks required for the access.
263 Tick recvAtomic(PacketPtr pkt);
266 * Snoop for the provided request in the cache and return the estimated
268 * @param pkt The memory request to snoop
269 * @return The number of ticks required for the snoop.
271 Tick recvAtomicSnoop(PacketPtr pkt);
274 * Performs the access specified by the request.
275 * @param pkt The request to perform.
276 * @param fromCpuSide from the CPU side port or the memory side port
278 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
280 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
281 bool deferred_response = false,
282 bool pending_downgrade = false);
283 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
285 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
286 bool already_copied, bool pending_inval);
289 * Sets the blk to the new state.
290 * @param blk The cache block being snooped.
291 * @param new_state The new coherence state for the block.
293 void handleSnoop(PacketPtr ptk, BlkType *blk,
294 bool is_timing, bool is_deferred, bool pending_inval);
297 * Create a writeback request for the given block.
298 * @param blk The block to writeback.
299 * @return The writeback request for the block.
301 PacketPtr writebackBlk(BlkType *blk);
305 void memInvalidate();
306 bool isDirty() const;
309 * Cache block visitor that writes back dirty cache blocks using
312 * \return Always returns true.
314 bool writebackVisitor(BlkType &blk);
316 * Cache block visitor that invalidates all blocks in the cache.
318 * @warn Dirty cache lines will not be written back to memory.
320 * \return Always returns true.
322 bool invalidateVisitor(BlkType &blk);
325 * Flush a cache line due to an uncacheable memory access to the
328 * @note This shouldn't normally happen, but we need to handle it
329 * since some architecture models don't implement cache
330 * maintenance operations. We won't even try to get a decent
331 * timing here since the line should have been flushed earlier by
332 * a cache maintenance operation.
334 void uncacheableFlush(PacketPtr pkt);
337 * Squash all requests associated with specified thread.
338 * intended for use by I-cache.
339 * @param threadNum The thread to squash.
341 void squash(int threadNum);
344 * Generate an appropriate downstream bus request packet for the
346 * @param cpu_pkt The upstream request that needs to be satisfied.
347 * @param blk The block currently in the cache corresponding to
348 * cpu_pkt (NULL if none).
349 * @param needsExclusive Indicates that an exclusive copy is required
350 * even if the request in cpu_pkt doesn't indicate that.
351 * @return A new Packet containing the request, or NULL if the
352 * current request in cpu_pkt should just be forwarded on.
354 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
355 bool needsExclusive) const;
358 * Return the next MSHR to service, either a pending miss from the
359 * mshrQueue, a buffered write from the write buffer, or something
360 * from the prefetcher. This function is responsible for
361 * prioritizing among those sources on the fly.
366 * Selects an outstanding request to service. Called when the
367 * cache gets granted the downstream bus in timing mode.
368 * @return The request to service, NULL if none found.
370 PacketPtr getTimingPacket();
373 * Marks a request as in service (sent on the bus). This can have side
374 * effect since storage for no response commands is deallocated once they
375 * are successfully sent.
376 * @param pkt The request that was sent on the bus.
378 void markInService(MSHR *mshr, PacketPtr pkt = 0);
381 * Return whether there are any outstanding misses.
383 bool outstandingMisses() const
385 return mshrQueue.allocated != 0;
388 CacheBlk *findBlock(Addr addr, bool is_secure) const {
389 return tags->findBlock(addr, is_secure);
392 bool inCache(Addr addr, bool is_secure) const {
393 return (tags->findBlock(addr, is_secure) != 0);
396 bool inMissQueue(Addr addr, bool is_secure) const {
397 return (mshrQueue.findMatch(addr, is_secure) != 0);
401 * Find next request ready time from among possible sources.
403 Tick nextMSHRReadyTime() const;
406 /** Instantiates a basic cache object. */
407 Cache(const Params *p);
409 /** Non-default destructor is needed to deallocate memory. */
414 /** serialize the state of the caches
415 * We currently don't support checkpointing cache state, so this panics.
417 virtual void serialize(std::ostream &os);
418 void unserialize(Checkpoint *cp, const std::string §ion);
421 #endif // __CACHE_HH__