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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
52 #ifndef __MEM_CACHE_CACHE_HH__
53 #define __MEM_CACHE_CACHE_HH__
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "enums/Clusivity.hh"
57 #include "mem/cache/base.hh"
58 #include "mem/cache/blk.hh"
59 #include "mem/cache/mshr.hh"
60 #include "mem/cache/tags/base.hh"
61 #include "params/Cache.hh"
62 #include "sim/eventq.hh"
68 * A template-policy based cache. The behavior of the cache can be altered by
69 * supplying different template policies. TagStore handles all tag and data
70 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
72 class Cache : public BaseCache
76 /** A typedef for a list of CacheBlk pointers. */
77 typedef std::list<CacheBlk*> BlkList;
82 * The CPU-side port extends the base cache slave port with access
83 * functions for functional, atomic and timing requests.
85 class CpuSidePort : public CacheSlavePort
89 // a pointer to our specific cache implementation
94 virtual bool recvTimingSnoopResp(PacketPtr pkt);
96 virtual bool recvTimingReq(PacketPtr pkt);
98 virtual Tick recvAtomic(PacketPtr pkt);
100 virtual void recvFunctional(PacketPtr pkt);
102 virtual AddrRangeList getAddrRanges() const;
106 CpuSidePort(const std::string &_name, Cache *_cache,
107 const std::string &_label);
112 * Override the default behaviour of sendDeferredPacket to enable
113 * the memory-side cache port to also send requests based on the
114 * current MSHR status. This queue has a pointer to our specific
115 * cache implementation and is used by the MemSidePort.
117 class CacheReqPacketQueue : public ReqPacketQueue
123 SnoopRespPacketQueue &snoopRespQueue;
127 CacheReqPacketQueue(Cache &cache, MasterPort &port,
128 SnoopRespPacketQueue &snoop_resp_queue,
129 const std::string &label) :
130 ReqPacketQueue(cache, port, label), cache(cache),
131 snoopRespQueue(snoop_resp_queue) { }
134 * Override the normal sendDeferredPacket and do not only
135 * consider the transmit list (used for responses), but also
138 virtual void sendDeferredPacket();
143 * The memory-side port extends the base cache master port with
144 * access functions for functional, atomic and timing snoops.
146 class MemSidePort : public CacheMasterPort
150 /** The cache-specific queue. */
151 CacheReqPacketQueue _reqQueue;
153 SnoopRespPacketQueue _snoopRespQueue;
155 // a pointer to our specific cache implementation
160 virtual void recvTimingSnoopReq(PacketPtr pkt);
162 virtual bool recvTimingResp(PacketPtr pkt);
164 virtual Tick recvAtomicSnoop(PacketPtr pkt);
166 virtual void recvFunctionalSnoop(PacketPtr pkt);
170 MemSidePort(const std::string &_name, Cache *_cache,
171 const std::string &_label);
174 /** Tag and data Storage */
178 BasePrefetcher *prefetcher;
180 /** Temporary cache block for occasional transitory use */
184 * This cache should allocate a block on a line-sized write miss.
186 const bool doFastWrites;
189 * Turn line-sized writes into WriteInvalidate transactions.
191 void promoteWholeLineWrites(PacketPtr pkt);
194 * Notify the prefetcher on every access, not just misses.
196 const bool prefetchOnAccess;
199 * Clusivity with respect to the upstream cache, determining if we
200 * fill into both this cache and the cache above on a miss. Note
201 * that we currently do not support strict clusivity policies.
203 const Enums::Clusivity clusivity;
206 * Determine if clean lines should be written back or not. In
207 * cases where a downstream cache is mostly inclusive we likely
208 * want it to act as a victim cache also for lines that have not
209 * been modified. Hence, we cannot simply drop the line (or send a
210 * clean evict), but rather need to send the actual data.
212 const bool writebackClean;
215 * Upstream caches need this packet until true is returned, so
216 * hold it for deletion until a subsequent call
218 std::unique_ptr<Packet> pendingDelete;
221 * Writebacks from the tempBlock, resulting on the response path
222 * in atomic mode, must happen after the call to recvAtomic has
223 * finished (for the right ordering of the packets). We therefore
224 * need to hold on to the packets, and have a method and an event
227 PacketPtr tempBlockWriteback;
230 * Send the outstanding tempBlock writeback. To be called after
231 * recvAtomic finishes in cases where the block we filled is in
232 * fact the tempBlock, and now needs to be written back.
234 void writebackTempBlockAtomic() {
235 assert(tempBlockWriteback != nullptr);
236 PacketList writebacks{tempBlockWriteback};
237 doWritebacksAtomic(writebacks);
238 tempBlockWriteback = nullptr;
242 * An event to writeback the tempBlock after recvAtomic
243 * finishes. To avoid other calls to recvAtomic getting in
244 * between, we create this event with a higher priority.
246 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
247 writebackTempBlockAtomicEvent;
250 * Store the outstanding requests that we are expecting snoop
251 * responses from so we can determine which snoop responses we
252 * generated and which ones were merely forwarded.
254 std::unordered_set<RequestPtr> outstandingSnoop;
257 * Does all the processing necessary to perform the provided request.
258 * @param pkt The memory request to perform.
259 * @param blk The cache block to be updated.
260 * @param lat The latency of the access.
261 * @param writebacks List for any writebacks that need to be performed.
262 * @return Boolean indicating whether the request was satisfied.
264 bool access(PacketPtr pkt, CacheBlk *&blk,
265 Cycles &lat, PacketList &writebacks);
268 *Handle doing the Compare and Swap function for SPARC.
270 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
273 * Find a block frame for new block at address addr targeting the
274 * given security space, assuming that the block is not currently
275 * in the cache. Append writebacks if any to provided packet
276 * list. Return free block frame. May return NULL if there are
277 * no replaceable blocks at the moment.
279 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
282 * Invalidate a cache block.
284 * @param blk Block to invalidate
286 void invalidateBlock(CacheBlk *blk);
289 * Populates a cache block and handles all outstanding requests for the
290 * satisfied fill request. This version takes two memory requests. One
291 * contains the fill data, the other is an optional target to satisfy.
292 * @param pkt The memory request with the fill data.
293 * @param blk The cache block if it already exists.
294 * @param writebacks List for any writebacks that need to be performed.
295 * @param allocate Whether to allocate a block or use the temp block
296 * @return Pointer to the new cache block.
298 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
299 PacketList &writebacks, bool allocate);
302 * Determine whether we should allocate on a fill or not. If this
303 * cache is mostly inclusive with regards to the upstream cache(s)
304 * we always allocate (for any non-forwarded and cacheable
305 * requests). In the case of a mostly exclusive cache, we allocate
306 * on fill if the packet did not come from a cache, thus if we:
307 * are dealing with a whole-line write (the latter behaves much
308 * like a writeback), the original target packet came from a
309 * non-caching source, or if we are performing a prefetch or LLSC.
311 * @param cmd Command of the incoming requesting packet
312 * @return Whether we should allocate on the fill
314 inline bool allocOnFill(MemCmd cmd) const override
316 return clusivity == Enums::mostly_incl ||
317 cmd == MemCmd::WriteLineReq ||
318 cmd == MemCmd::ReadReq ||
319 cmd == MemCmd::WriteReq ||
325 * Performs the access specified by the request.
326 * @param pkt The request to perform.
327 * @return The result of the access.
329 bool recvTimingReq(PacketPtr pkt);
332 * Insert writebacks into the write buffer
334 void doWritebacks(PacketList& writebacks, Tick forward_time);
337 * Send writebacks down the memory hierarchy in atomic mode
339 void doWritebacksAtomic(PacketList& writebacks);
342 * Handles a response (cache line fill/write ack) from the bus.
343 * @param pkt The response packet
345 void recvTimingResp(PacketPtr pkt);
348 * Snoops bus transactions to maintain coherence.
349 * @param pkt The current bus transaction.
351 void recvTimingSnoopReq(PacketPtr pkt);
354 * Handle a snoop response.
355 * @param pkt Snoop response packet
357 void recvTimingSnoopResp(PacketPtr pkt);
360 * Performs the access specified by the request.
361 * @param pkt The request to perform.
362 * @return The number of ticks required for the access.
364 Tick recvAtomic(PacketPtr pkt);
367 * Snoop for the provided request in the cache and return the estimated
369 * @param pkt The memory request to snoop
370 * @return The number of ticks required for the snoop.
372 Tick recvAtomicSnoop(PacketPtr pkt);
375 * Performs the access specified by the request.
376 * @param pkt The request to perform.
377 * @param fromCpuSide from the CPU side port or the memory side port
379 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
381 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
382 bool deferred_response = false,
383 bool pending_downgrade = false);
384 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
386 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
387 bool already_copied, bool pending_inval);
390 * Perform an upward snoop if needed, and update the block state
391 * (possibly invalidating the block). Also create a response if required.
393 * @param pkt Snoop packet
394 * @param blk Cache block being snooped
395 * @param is_timing Timing or atomic for the response
396 * @param is_deferred Is this a deferred snoop or not?
397 * @param pending_inval Do we have a pending invalidation?
399 * @return The snoop delay incurred by the upwards snoop
401 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
402 bool is_timing, bool is_deferred, bool pending_inval);
405 * Create a writeback request for the given block.
406 * @param blk The block to writeback.
407 * @return The writeback request for the block.
409 PacketPtr writebackBlk(CacheBlk *blk);
412 * Create a CleanEvict request for the given block.
413 * @param blk The block to evict.
414 * @return The CleanEvict request for the block.
416 PacketPtr cleanEvictBlk(CacheBlk *blk);
419 void memWriteback() override;
420 void memInvalidate() override;
421 bool isDirty() const override;
424 * Cache block visitor that writes back dirty cache blocks using
427 * \return Always returns true.
429 bool writebackVisitor(CacheBlk &blk);
431 * Cache block visitor that invalidates all blocks in the cache.
433 * @warn Dirty cache lines will not be written back to memory.
435 * \return Always returns true.
437 bool invalidateVisitor(CacheBlk &blk);
440 * Generate an appropriate downstream bus request packet for the
442 * @param cpu_pkt The upstream request that needs to be satisfied.
443 * @param blk The block currently in the cache corresponding to
444 * cpu_pkt (NULL if none).
445 * @param needsExclusive Indicates that an exclusive copy is required
446 * even if the request in cpu_pkt doesn't indicate that.
447 * @return A new Packet containing the request, or NULL if the
448 * current request in cpu_pkt should just be forwarded on.
450 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
451 bool needsExclusive) const;
454 * Return the next MSHR to service, either a pending miss from the
455 * mshrQueue, a buffered write from the write buffer, or something
456 * from the prefetcher. This function is responsible for
457 * prioritizing among those sources on the fly.
462 * Send up a snoop request and find cached copies. If cached copies are
463 * found, set the BLOCK_CACHED flag in pkt.
465 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const;
468 * Selects an outstanding request to service. Called when the
469 * cache gets granted the downstream bus in timing mode.
470 * @return The request to service, NULL if none found.
472 PacketPtr getTimingPacket();
475 * Marks a request as in service (sent on the bus). This can have
476 * side effect since storage for no response commands is
477 * deallocated once they are successfully sent. Also remember if
478 * we are expecting a dirty response from another cache,
479 * effectively making this MSHR the ordering point.
481 void markInService(MSHR *mshr, bool pending_dirty_resp);
484 * Return whether there are any outstanding misses.
486 bool outstandingMisses() const
488 return mshrQueue.allocated != 0;
491 CacheBlk *findBlock(Addr addr, bool is_secure) const {
492 return tags->findBlock(addr, is_secure);
495 bool inCache(Addr addr, bool is_secure) const override {
496 return (tags->findBlock(addr, is_secure) != 0);
499 bool inMissQueue(Addr addr, bool is_secure) const override {
500 return (mshrQueue.findMatch(addr, is_secure) != 0);
504 * Find next request ready time from among possible sources.
506 Tick nextMSHRReadyTime() const;
509 /** Instantiates a basic cache object. */
510 Cache(const CacheParams *p);
512 /** Non-default destructor is needed to deallocate memory. */
515 void regStats() override;
517 /** serialize the state of the caches
518 * We currently don't support checkpointing cache state, so this panics.
520 void serialize(CheckpointOut &cp) const override;
521 void unserialize(CheckpointIn &cp) override;
525 * Wrap a method and present it as a cache block visitor.
527 * For example the forEachBlk method in the tag arrays expects a
528 * callable object/function as their parameter. This class wraps a
529 * method in an object and presents callable object that adheres to
530 * the cache block visitor protocol.
532 class CacheBlkVisitorWrapper : public CacheBlkVisitor
535 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
537 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
538 : cache(_cache), visitor(_visitor) {}
540 bool operator()(CacheBlk &blk) override {
541 return (cache.*visitor)(blk);
550 * Cache block visitor that determines if there are dirty blocks in a
553 * Use with the forEachBlk method in the tag array to determine if the
554 * array contains dirty blocks.
556 class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
559 CacheBlkIsDirtyVisitor()
562 bool operator()(CacheBlk &blk) override {
572 * Does the array contain a dirty line?
574 * \return true if yes, false otherwise.
576 bool isDirty() const { return _isDirty; };
582 #endif // __MEM_CACHE_CACHE_HH__