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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/misc.hh" // fatal, panic, and warn
44 #include "mem/cache/base.hh"
45 #include "mem/cache/blk.hh"
46 #include "mem/cache/mshr.hh"
48 #include "sim/eventq.hh"
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
58 template <class TagStore>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
69 class CpuSidePort : public CachePort
72 CpuSidePort(const std::string &_name,
73 Cache<TagStore> *_cache,
74 const std::string &_label);
76 // BaseCache::CachePort just has a BaseCache *; this function
77 // lets us get back the type info we lost when we stored the
78 // cache pointer there.
79 Cache<TagStore> *myCache() {
80 return static_cast<Cache<TagStore> *>(cache);
83 virtual void getDeviceAddressRanges(AddrRangeList &resp,
86 virtual bool recvTiming(PacketPtr pkt);
88 virtual Tick recvAtomic(PacketPtr pkt);
90 virtual void recvFunctional(PacketPtr pkt);
93 class MemSidePort : public CachePort
96 MemSidePort(const std::string &_name,
97 Cache<TagStore> *_cache,
98 const std::string &_label);
100 // BaseCache::CachePort just has a BaseCache *; this function
101 // lets us get back the type info we lost when we stored the
102 // cache pointer there.
103 Cache<TagStore> *myCache() {
104 return static_cast<Cache<TagStore> *>(cache);
109 void processSendEvent();
111 virtual void getDeviceAddressRanges(AddrRangeList &resp,
114 virtual bool recvTiming(PacketPtr pkt);
116 virtual void recvRetry();
118 virtual Tick recvAtomic(PacketPtr pkt);
120 virtual void recvFunctional(PacketPtr pkt);
122 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
126 /** Tag and data Storage */
130 BasePrefetcher *prefetcher;
132 /** Temporary cache block for occasional transitory use */
136 * This cache should allocate a block on a line-sized write miss.
138 const bool doFastWrites;
141 * Notify the prefetcher on every access, not just misses.
143 const bool prefetchOnAccess;
146 * Does all the processing necessary to perform the provided request.
147 * @param pkt The memory request to perform.
148 * @param lat The latency of the access.
149 * @param writebacks List for any writebacks that need to be performed.
150 * @param update True if the replacement data should be updated.
151 * @return Boolean indicating whether the request was satisfied.
153 bool access(PacketPtr pkt, BlkType *&blk,
154 int &lat, PacketList &writebacks);
157 *Handle doing the Compare and Swap function for SPARC.
159 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
162 * Find a block frame for new block at address addr, assuming that
163 * the block is not currently in the cache. Append writebacks if
164 * any to provided packet list. Return free block frame. May
165 * return NULL if there are no replaceable blocks at the moment.
167 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
170 * Populates a cache block and handles all outstanding requests for the
171 * satisfied fill request. This version takes two memory requests. One
172 * contains the fill data, the other is an optional target to satisfy.
173 * @param pkt The memory request with the fill data.
174 * @param blk The cache block if it already exists.
175 * @param writebacks List for any writebacks that need to be performed.
176 * @return Pointer to the new cache block.
178 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
179 PacketList &writebacks);
181 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
182 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
184 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
185 bool already_copied, bool pending_inval);
188 * Sets the blk to the new state.
189 * @param blk The cache block being snooped.
190 * @param new_state The new coherence state for the block.
192 void handleSnoop(PacketPtr ptk, BlkType *blk,
193 bool is_timing, bool is_deferred, bool pending_inval);
196 * Create a writeback request for the given block.
197 * @param blk The block to writeback.
198 * @return The writeback request for the block.
200 PacketPtr writebackBlk(BlkType *blk);
203 /** Instantiates a basic cache object. */
204 Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
206 virtual Port *getPort(const std::string &if_name, int idx = -1);
207 virtual void deletePortRefs(Port *p);
212 * Performs the access specified by the request.
213 * @param pkt The request to perform.
214 * @return The result of the access.
216 bool timingAccess(PacketPtr pkt);
219 * Performs the access specified by the request.
220 * @param pkt The request to perform.
221 * @return The result of the access.
223 Tick atomicAccess(PacketPtr pkt);
226 * Performs the access specified by the request.
227 * @param pkt The request to perform.
228 * @return The result of the access.
230 void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
231 CachePort *otherSidePort);
234 * Handles a response (cache line fill/write ack) from the bus.
235 * @param pkt The request being responded to.
237 void handleResponse(PacketPtr pkt);
240 * Snoops bus transactions to maintain coherence.
241 * @param pkt The current bus transaction.
243 void snoopTiming(PacketPtr pkt);
246 * Snoop for the provided request in the cache and return the estimated
247 * time of completion.
248 * @param pkt The memory request to snoop
249 * @return The estimated completion time.
251 Tick snoopAtomic(PacketPtr pkt);
254 * Squash all requests associated with specified thread.
255 * intended for use by I-cache.
256 * @param threadNum The thread to squash.
258 void squash(int threadNum);
261 * Generate an appropriate downstream bus request packet for the
263 * @param cpu_pkt The upstream request that needs to be satisfied.
264 * @param blk The block currently in the cache corresponding to
265 * cpu_pkt (NULL if none).
266 * @param needsExclusive Indicates that an exclusive copy is required
267 * even if the request in cpu_pkt doesn't indicate that.
268 * @return A new Packet containing the request, or NULL if the
269 * current request in cpu_pkt should just be forwarded on.
271 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
272 bool needsExclusive);
275 * Return the next MSHR to service, either a pending miss from the
276 * mshrQueue, a buffered write from the write buffer, or something
277 * from the prefetcher. This function is responsible for
278 * prioritizing among those sources on the fly.
283 * Selects an outstanding request to service. Called when the
284 * cache gets granted the downstream bus in timing mode.
285 * @return The request to service, NULL if none found.
287 PacketPtr getTimingPacket();
290 * Marks a request as in service (sent on the bus). This can have side
291 * effect since storage for no response commands is deallocated once they
292 * are successfully sent.
293 * @param pkt The request that was sent on the bus.
295 void markInService(MSHR *mshr);
298 * Perform the given writeback request.
299 * @param pkt The writeback request.
301 void doWriteback(PacketPtr pkt);
304 * Return whether there are any outstanding misses.
306 bool outstandingMisses() const
308 return mshrQueue.allocated != 0;
311 CacheBlk *findBlock(Addr addr) {
312 return tags->findBlock(addr);
315 bool inCache(Addr addr) {
316 return (tags->findBlock(addr) != 0);
319 bool inMissQueue(Addr addr) {
320 return (mshrQueue.findMatch(addr) != 0);
324 * Find next request ready time from among possible sources.
326 Tick nextMSHRReadyTime();
329 #endif // __CACHE_HH__