src/mem/cache/cache.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Dave Greene
  42  *          Steve Reinhardt
  43  *          Ron Dreslinski
  44  */
  45
  46 /**
  47  * @file
  48  * Describes a cache based on template policies.
  49  */
  50
  51 #ifndef __CACHE_HH__
  52 #define __CACHE_HH__
  53
  54 #include "base/misc.hh" // fatal, panic, and warn
  55 #include "mem/cache/base.hh"
  56 #include "mem/cache/blk.hh"
  57 #include "mem/cache/mshr.hh"
  58 #include "sim/eventq.hh"
  59
  60 //Forward decleration
  61 class BasePrefetcher;
  62
  63 /**
  64  * A template-policy based cache. The behavior of the cache can be altered by
  65  * supplying different template policies. TagStore handles all tag and data
  66  * storage @sa TagStore.
  67  */
  68 template <class TagStore>
  69 class Cache : public BaseCache
  70 {
  71   public:
  72     /** Define the type of cache block to use. */
  73     typedef typename TagStore::BlkType BlkType;
  74     /** A typedef for a list of BlkType pointers. */
  75     typedef typename TagStore::BlkList BlkList;
  76
  77   protected:
  78
  79     class CpuSidePort : public CachePort
  80     {
  81       public:
  82         CpuSidePort(const std::string &_name,
  83                     Cache<TagStore> *_cache,
  84                     const std::string &_label);
  85
  86         // BaseCache::CachePort just has a BaseCache *; this function
  87         // lets us get back the type info we lost when we stored the
  88         // cache pointer there.
  89         Cache<TagStore> *myCache() {
  90             return static_cast<Cache<TagStore> *>(cache);
  91         }
  92
  93         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  94                                             bool &snoop);
  95
  96         virtual bool recvTiming(PacketPtr pkt);
  97
  98         virtual Tick recvAtomic(PacketPtr pkt);
  99
 100         virtual void recvFunctional(PacketPtr pkt);
 101     };
 102
 103     class MemSidePort : public CachePort
 104     {
 105       public:
 106         MemSidePort(const std::string &_name,
 107                     Cache<TagStore> *_cache,
 108                     const std::string &_label);
 109
 110         // BaseCache::CachePort just has a BaseCache *; this function
 111         // lets us get back the type info we lost when we stored the
 112         // cache pointer there.
 113         Cache<TagStore> *myCache() {
 114             return static_cast<Cache<TagStore> *>(cache);
 115         }
 116
 117         void sendPacket();
 118
 119         void processSendEvent();
 120
 121         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 122                                             bool &snoop);
 123
 124         virtual bool recvTiming(PacketPtr pkt);
 125
 126         virtual void recvRetry();
 127
 128         virtual Tick recvAtomic(PacketPtr pkt);
 129
 130         virtual void recvFunctional(PacketPtr pkt);
 131
 132         typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
 133                 SendEvent;
 134     };
 135
 136     /** Tag and data Storage */
 137     TagStore *tags;
 138
 139     /** Prefetcher */
 140     BasePrefetcher *prefetcher;
 141
 142     /** Temporary cache block for occasional transitory use */
 143     BlkType *tempBlock;
 144
 145     /**
 146      * This cache should allocate a block on a line-sized write miss.
 147      */
 148     const bool doFastWrites;
 149
 150     /**
 151      * Notify the prefetcher on every access, not just misses.
 152      */
 153     const bool prefetchOnAccess;
 154
 155     /**
 156      * Does all the processing necessary to perform the provided request.
 157      * @param pkt The memory request to perform.
 158      * @param lat The latency of the access.
 159      * @param writebacks List for any writebacks that need to be performed.
 160      * @param update True if the replacement data should be updated.
 161      * @return Boolean indicating whether the request was satisfied.
 162      */
 163     bool access(PacketPtr pkt, BlkType *&blk,
 164                 int &lat, PacketList &writebacks);
 165
 166     /**
 167      *Handle doing the Compare and Swap function for SPARC.
 168      */
 169     void cmpAndSwap(BlkType *blk, PacketPtr pkt);
 170
 171     /**
 172      * Find a block frame for new block at address addr, assuming that
 173      * the block is not currently in the cache.  Append writebacks if
 174      * any to provided packet list.  Return free block frame.  May
 175      * return NULL if there are no replaceable blocks at the moment.
 176      */
 177     BlkType *allocateBlock(Addr addr, PacketList &writebacks);
 178
 179     /**
 180      * Populates a cache block and handles all outstanding requests for the
 181      * satisfied fill request. This version takes two memory requests. One
 182      * contains the fill data, the other is an optional target to satisfy.
 183      * @param pkt The memory request with the fill data.
 184      * @param blk The cache block if it already exists.
 185      * @param writebacks List for any writebacks that need to be performed.
 186      * @return Pointer to the new cache block.
 187      */
 188     BlkType *handleFill(PacketPtr pkt, BlkType *blk,
 189                         PacketList &writebacks);
 190
 191     void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
 192                                bool deferred_response = false,
 193                                bool pending_downgrade = false);
 194     bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
 195
 196     void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
 197                                 bool already_copied, bool pending_inval);
 198
 199     /**
 200      * Sets the blk to the new state.
 201      * @param blk The cache block being snooped.
 202      * @param new_state The new coherence state for the block.
 203      */
 204     void handleSnoop(PacketPtr ptk, BlkType *blk,
 205                      bool is_timing, bool is_deferred, bool pending_inval);
 206
 207     /**
 208      * Create a writeback request for the given block.
 209      * @param blk The block to writeback.
 210      * @return The writeback request for the block.
 211      */
 212     PacketPtr writebackBlk(BlkType *blk);
 213
 214   public:
 215     /** Instantiates a basic cache object. */
 216     Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
 217
 218     virtual Port *getPort(const std::string &if_name, int idx = -1);
 219
 220     void regStats();
 221
 222     /**
 223      * Performs the access specified by the request.
 224      * @param pkt The request to perform.
 225      * @return The result of the access.
 226      */
 227     bool timingAccess(PacketPtr pkt);
 228
 229     /**
 230      * Performs the access specified by the request.
 231      * @param pkt The request to perform.
 232      * @return The result of the access.
 233      */
 234     Tick atomicAccess(PacketPtr pkt);
 235
 236     /**
 237      * Performs the access specified by the request.
 238      * @param pkt The request to perform.
 239      * @param fromCpuSide from the CPU side port or the memory side port
 240      */
 241     void functionalAccess(PacketPtr pkt, bool fromCpuSide);
 242
 243     /**
 244      * Handles a response (cache line fill/write ack) from the bus.
 245      * @param pkt The request being responded to.
 246      */
 247     void handleResponse(PacketPtr pkt);
 248
 249     /**
 250      * Snoops bus transactions to maintain coherence.
 251      * @param pkt The current bus transaction.
 252      */
 253     void snoopTiming(PacketPtr pkt);
 254
 255     /**
 256      * Snoop for the provided request in the cache and return the estimated
 257      * time of completion.
 258      * @param pkt The memory request to snoop
 259      * @return The estimated completion time.
 260      */
 261     Tick snoopAtomic(PacketPtr pkt);
 262
 263     /**
 264      * Squash all requests associated with specified thread.
 265      * intended for use by I-cache.
 266      * @param threadNum The thread to squash.
 267      */
 268     void squash(int threadNum);
 269
 270     /**
 271      * Generate an appropriate downstream bus request packet for the
 272      * given parameters.
 273      * @param cpu_pkt  The upstream request that needs to be satisfied.
 274      * @param blk The block currently in the cache corresponding to
 275      * cpu_pkt (NULL if none).
 276      * @param needsExclusive  Indicates that an exclusive copy is required
 277      * even if the request in cpu_pkt doesn't indicate that.
 278      * @return A new Packet containing the request, or NULL if the
 279      * current request in cpu_pkt should just be forwarded on.
 280      */
 281     PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
 282                            bool needsExclusive);
 283
 284     /**
 285      * Return the next MSHR to service, either a pending miss from the
 286      * mshrQueue, a buffered write from the write buffer, or something
 287      * from the prefetcher.  This function is responsible for
 288      * prioritizing among those sources on the fly.
 289      */
 290     MSHR *getNextMSHR();
 291
 292     /**
 293      * Selects an outstanding request to service.  Called when the
 294      * cache gets granted the downstream bus in timing mode.
 295      * @return The request to service, NULL if none found.
 296      */
 297     PacketPtr getTimingPacket();
 298
 299     /**
 300      * Marks a request as in service (sent on the bus). This can have side
 301      * effect since storage for no response commands is deallocated once they
 302      * are successfully sent.
 303      * @param pkt The request that was sent on the bus.
 304      */
 305     void markInService(MSHR *mshr, PacketPtr pkt = 0);
 306
 307     /**
 308      * Perform the given writeback request.
 309      * @param pkt The writeback request.
 310      */
 311     void doWriteback(PacketPtr pkt);
 312
 313     /**
 314      * Return whether there are any outstanding misses.
 315      */
 316     bool outstandingMisses() const
 317     {
 318         return mshrQueue.allocated != 0;
 319     }
 320
 321     CacheBlk *findBlock(Addr addr) {
 322         return tags->findBlock(addr);
 323     }
 324
 325     bool inCache(Addr addr) {
 326         return (tags->findBlock(addr) != 0);
 327     }
 328
 329     bool inMissQueue(Addr addr) {
 330         return (mshrQueue.findMatch(addr) != 0);
 331     }
 332
 333     /**
 334      * Find next request ready time from among possible sources.
 335      */
 336     Tick nextMSHRReadyTime();
 337 };
 338
 339 #endif // __CACHE_HH__