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40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
52 #ifndef __MEM_CACHE_CACHE_HH__
53 #define __MEM_CACHE_CACHE_HH__
55 #include <unordered_set>
57 #include "base/logging.hh" // fatal, panic, and warn
58 #include "enums/Clusivity.hh"
59 #include "mem/cache/base.hh"
60 #include "mem/cache/blk.hh"
61 #include "mem/cache/mshr.hh"
62 #include "mem/cache/tags/base.hh"
63 #include "params/Cache.hh"
64 #include "sim/eventq.hh"
70 * A template-policy based cache. The behavior of the cache can be altered by
71 * supplying different template policies. TagStore handles all tag and data
72 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
74 class Cache : public BaseCache
79 * The CPU-side port extends the base cache slave port with access
80 * functions for functional, atomic and timing requests.
82 class CpuSidePort : public CacheSlavePort
86 // a pointer to our specific cache implementation
91 virtual bool recvTimingSnoopResp(PacketPtr pkt);
93 virtual bool tryTiming(PacketPtr pkt);
95 virtual bool recvTimingReq(PacketPtr pkt);
97 virtual Tick recvAtomic(PacketPtr pkt);
99 virtual void recvFunctional(PacketPtr pkt);
101 virtual AddrRangeList getAddrRanges() const;
105 CpuSidePort(const std::string &_name, Cache *_cache,
106 const std::string &_label);
111 * Override the default behaviour of sendDeferredPacket to enable
112 * the memory-side cache port to also send requests based on the
113 * current MSHR status. This queue has a pointer to our specific
114 * cache implementation and is used by the MemSidePort.
116 class CacheReqPacketQueue : public ReqPacketQueue
122 SnoopRespPacketQueue &snoopRespQueue;
126 CacheReqPacketQueue(Cache &cache, MasterPort &port,
127 SnoopRespPacketQueue &snoop_resp_queue,
128 const std::string &label) :
129 ReqPacketQueue(cache, port, label), cache(cache),
130 snoopRespQueue(snoop_resp_queue) { }
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
137 virtual void sendDeferredPacket();
140 * Check if there is a conflicting snoop response about to be
141 * send out, and if so simply stall any requests, and schedule
142 * a send event at the same time as the next snoop response is
145 bool checkConflictingSnoop(Addr addr)
147 if (snoopRespQueue.hasAddr(addr)) {
148 DPRINTF(CachePort, "Waiting for snoop response to be "
150 Tick when = snoopRespQueue.deferredPacketReadyTime();
151 schedSendEvent(when);
159 * The memory-side port extends the base cache master port with
160 * access functions for functional, atomic and timing snoops.
162 class MemSidePort : public CacheMasterPort
166 /** The cache-specific queue. */
167 CacheReqPacketQueue _reqQueue;
169 SnoopRespPacketQueue _snoopRespQueue;
171 // a pointer to our specific cache implementation
176 virtual void recvTimingSnoopReq(PacketPtr pkt);
178 virtual bool recvTimingResp(PacketPtr pkt);
180 virtual Tick recvAtomicSnoop(PacketPtr pkt);
182 virtual void recvFunctionalSnoop(PacketPtr pkt);
186 MemSidePort(const std::string &_name, Cache *_cache,
187 const std::string &_label);
190 /** Tag and data Storage */
194 BasePrefetcher *prefetcher;
196 /** Temporary cache block for occasional transitory use */
200 * This cache should allocate a block on a line-sized write miss.
202 const bool doFastWrites;
205 * Turn line-sized writes into WriteInvalidate transactions.
207 void promoteWholeLineWrites(PacketPtr pkt);
210 * Notify the prefetcher on every access, not just misses.
212 const bool prefetchOnAccess;
215 * Clusivity with respect to the upstream cache, determining if we
216 * fill into both this cache and the cache above on a miss. Note
217 * that we currently do not support strict clusivity policies.
219 const Enums::Clusivity clusivity;
222 * Determine if clean lines should be written back or not. In
223 * cases where a downstream cache is mostly inclusive we likely
224 * want it to act as a victim cache also for lines that have not
225 * been modified. Hence, we cannot simply drop the line (or send a
226 * clean evict), but rather need to send the actual data.
228 const bool writebackClean;
231 * Upstream caches need this packet until true is returned, so
232 * hold it for deletion until a subsequent call
234 std::unique_ptr<Packet> pendingDelete;
237 * Writebacks from the tempBlock, resulting on the response path
238 * in atomic mode, must happen after the call to recvAtomic has
239 * finished (for the right ordering of the packets). We therefore
240 * need to hold on to the packets, and have a method and an event
243 PacketPtr tempBlockWriteback;
246 * Send the outstanding tempBlock writeback. To be called after
247 * recvAtomic finishes in cases where the block we filled is in
248 * fact the tempBlock, and now needs to be written back.
250 void writebackTempBlockAtomic() {
251 assert(tempBlockWriteback != nullptr);
252 PacketList writebacks{tempBlockWriteback};
253 doWritebacksAtomic(writebacks);
254 tempBlockWriteback = nullptr;
258 * An event to writeback the tempBlock after recvAtomic
259 * finishes. To avoid other calls to recvAtomic getting in
260 * between, we create this event with a higher priority.
262 EventFunctionWrapper writebackTempBlockAtomicEvent;
265 * Store the outstanding requests that we are expecting snoop
266 * responses from so we can determine which snoop responses we
267 * generated and which ones were merely forwarded.
269 std::unordered_set<RequestPtr> outstandingSnoop;
272 * Does all the processing necessary to perform the provided request.
273 * @param pkt The memory request to perform.
274 * @param blk The cache block to be updated.
275 * @param lat The latency of the access.
276 * @param writebacks List for any writebacks that need to be performed.
277 * @return Boolean indicating whether the request was satisfied.
279 bool access(PacketPtr pkt, CacheBlk *&blk,
280 Cycles &lat, PacketList &writebacks);
283 *Handle doing the Compare and Swap function for SPARC.
285 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
288 * Find a block frame for new block at address addr targeting the
289 * given security space, assuming that the block is not currently
290 * in the cache. Append writebacks if any to provided packet
291 * list. Return free block frame. May return nullptr if there are
292 * no replaceable blocks at the moment.
294 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
297 * Invalidate a cache block.
299 * @param blk Block to invalidate
301 void invalidateBlock(CacheBlk *blk);
304 * Maintain the clusivity of this cache by potentially
305 * invalidating a block. This method works in conjunction with
306 * satisfyRequest, but is separate to allow us to handle all MSHR
307 * targets before potentially dropping a block.
309 * @param from_cache Whether we have dealt with a packet from a cache
310 * @param blk The block that should potentially be dropped
312 void maintainClusivity(bool from_cache, CacheBlk *blk);
315 * Populates a cache block and handles all outstanding requests for the
316 * satisfied fill request. This version takes two memory requests. One
317 * contains the fill data, the other is an optional target to satisfy.
318 * @param pkt The memory request with the fill data.
319 * @param blk The cache block if it already exists.
320 * @param writebacks List for any writebacks that need to be performed.
321 * @param allocate Whether to allocate a block or use the temp block
322 * @return Pointer to the new cache block.
324 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
325 PacketList &writebacks, bool allocate);
328 * Determine whether we should allocate on a fill or not. If this
329 * cache is mostly inclusive with regards to the upstream cache(s)
330 * we always allocate (for any non-forwarded and cacheable
331 * requests). In the case of a mostly exclusive cache, we allocate
332 * on fill if the packet did not come from a cache, thus if we:
333 * are dealing with a whole-line write (the latter behaves much
334 * like a writeback), the original target packet came from a
335 * non-caching source, or if we are performing a prefetch or LLSC.
337 * @param cmd Command of the incoming requesting packet
338 * @return Whether we should allocate on the fill
340 inline bool allocOnFill(MemCmd cmd) const override
342 return clusivity == Enums::mostly_incl ||
343 cmd == MemCmd::WriteLineReq ||
344 cmd == MemCmd::ReadReq ||
345 cmd == MemCmd::WriteReq ||
351 * Handle a timing request that hit in the cache
353 * @param ptk The request packet
354 * @param blk The referenced block
355 * @param request_time The tick at which the block lookup is compete
357 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time);
360 * Handle a timing request that missed in the cache
362 * @param ptk The request packet
363 * @param blk The referenced block
364 * @param forward_time The tick at which we can process dependent requests
365 * @param request_time The tick at which the block lookup is compete
367 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time,
371 * Performs the access specified by the request.
372 * @param pkt The request to perform.
374 void recvTimingReq(PacketPtr pkt);
377 * Insert writebacks into the write buffer
379 void doWritebacks(PacketList& writebacks, Tick forward_time);
382 * Send writebacks down the memory hierarchy in atomic mode
384 void doWritebacksAtomic(PacketList& writebacks);
387 * Handling the special case of uncacheable write responses to
388 * make recvTimingResp less cluttered.
390 void handleUncacheableWriteResp(PacketPtr pkt);
393 * Service non-deferred MSHR targets using the received response
395 * Iterates through the list of targets that can be serviced with
396 * the current response. Any writebacks that need to performed
397 * must be appended to the writebacks parameter.
399 * @param mshr The MSHR that corresponds to the reponse
400 * @param pkt The response packet
401 * @param blk The reference block
402 * @param writebacks List of writebacks that need to be performed
404 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
405 PacketList& writebacks);
408 * Handles a response (cache line fill/write ack) from the bus.
409 * @param pkt The response packet
411 void recvTimingResp(PacketPtr pkt);
414 * Snoops bus transactions to maintain coherence.
415 * @param pkt The current bus transaction.
417 void recvTimingSnoopReq(PacketPtr pkt);
420 * Handle a snoop response.
421 * @param pkt Snoop response packet
423 void recvTimingSnoopResp(PacketPtr pkt);
427 * Handle a request in atomic mode that missed in this cache
429 * Creates a downstream request, sends it to the memory below and
430 * handles the response. As we are in atomic mode all operations
431 * are performed immediately.
433 * @param pkt The packet with the requests
434 * @param blk The referenced block
435 * @parma writebacks A list with packets for any performed writebacks
436 * @return Cycles for handling the request
438 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
439 PacketList &writebacks);
442 * Performs the access specified by the request.
443 * @param pkt The request to perform.
444 * @return The number of ticks required for the access.
446 Tick recvAtomic(PacketPtr pkt);
449 * Snoop for the provided request in the cache and return the estimated
451 * @param pkt The memory request to snoop
452 * @return The number of ticks required for the snoop.
454 Tick recvAtomicSnoop(PacketPtr pkt);
457 * Performs the access specified by the request.
458 * @param pkt The request to perform.
459 * @param fromCpuSide from the CPU side port or the memory side port
461 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
464 * Perform any necessary updates to the block and perform any data
465 * exchange between the packet and the block. The flags of the
466 * packet are also set accordingly.
468 * @param pkt Request packet from upstream that hit a block
469 * @param blk Cache block that the packet hit
470 * @param deferred_response Whether this hit is to block that
472 * @param pending_downgrade Whether the writable flag is to be removed
474 * @return True if the block is to be invalidated
476 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
477 bool deferred_response = false,
478 bool pending_downgrade = false);
480 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
481 bool already_copied, bool pending_inval);
484 * Perform an upward snoop if needed, and update the block state
485 * (possibly invalidating the block). Also create a response if required.
487 * @param pkt Snoop packet
488 * @param blk Cache block being snooped
489 * @param is_timing Timing or atomic for the response
490 * @param is_deferred Is this a deferred snoop or not?
491 * @param pending_inval Do we have a pending invalidation?
493 * @return The snoop delay incurred by the upwards snoop
495 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
496 bool is_timing, bool is_deferred, bool pending_inval);
499 * Evict a cache block.
501 * Performs a writeback if necesssary and invalidates the block
503 * @param blk Block to invalidate
504 * @return A packet with the writeback, can be nullptr
506 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk);
509 * Evict a cache block.
511 * Performs a writeback if necesssary and invalidates the block
513 * @param blk Block to invalidate
514 * @param writebacks Return a list of packets with writebacks
516 virtual void evictBlock(CacheBlk *blk, PacketList &writebacks);
519 * Create a writeback request for the given block.
520 * @param blk The block to writeback.
521 * @return The writeback request for the block.
523 PacketPtr writebackBlk(CacheBlk *blk);
526 * Create a writeclean request for the given block.
527 * @param blk The block to write clean
528 * @param dest The destination of this clean operation
529 * @return The write clean packet for the block.
531 PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
534 * Create a CleanEvict request for the given block.
535 * @param blk The block to evict.
536 * @return The CleanEvict request for the block.
538 PacketPtr cleanEvictBlk(CacheBlk *blk);
541 void memWriteback() override;
542 void memInvalidate() override;
543 bool isDirty() const override;
546 * Cache block visitor that writes back dirty cache blocks using
549 * \return Always returns true.
551 bool writebackVisitor(CacheBlk &blk);
553 * Cache block visitor that invalidates all blocks in the cache.
555 * @warn Dirty cache lines will not be written back to memory.
557 * \return Always returns true.
559 bool invalidateVisitor(CacheBlk &blk);
562 * Create an appropriate downstream bus request packet for the
564 * @param cpu_pkt The miss that needs to be satisfied.
565 * @param blk The block currently in the cache corresponding to
566 * cpu_pkt (nullptr if none).
567 * @param needsWritable Indicates that the block must be writable
568 * even if the request in cpu_pkt doesn't indicate that.
569 * @return A new Packet containing the request, or nullptr if the
570 * current request in cpu_pkt should just be forwarded on.
572 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
573 bool needsWritable) const;
576 * Return the next queue entry to service, either a pending miss
577 * from the MSHR queue, a buffered write from the write buffer, or
578 * something from the prefetcher. This function is responsible
579 * for prioritizing among those sources on the fly.
581 QueueEntry* getNextQueueEntry();
584 * Send up a snoop request and find cached copies. If cached copies are
585 * found, set the BLOCK_CACHED flag in pkt.
587 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const;
590 * Return whether there are any outstanding misses.
592 bool outstandingMisses() const
594 return !mshrQueue.isEmpty();
597 CacheBlk *findBlock(Addr addr, bool is_secure) const {
598 return tags->findBlock(addr, is_secure);
601 bool inCache(Addr addr, bool is_secure) const override {
602 return (tags->findBlock(addr, is_secure) != 0);
605 bool inMissQueue(Addr addr, bool is_secure) const override {
606 return (mshrQueue.findMatch(addr, is_secure) != 0);
610 * Find next request ready time from among possible sources.
612 Tick nextQueueReadyTime() const;
615 /** Instantiates a basic cache object. */
616 Cache(const CacheParams *p);
618 /** Non-default destructor is needed to deallocate memory. */
621 void regStats() override;
624 * Take an MSHR, turn it into a suitable downstream packet, and
625 * send it out. This construct allows a queue entry to choose a suitable
626 * approach based on its type.
628 * @param mshr The MSHR to turn into a packet and send
629 * @return True if the port is waiting for a retry
631 bool sendMSHRQueuePacket(MSHR* mshr);
634 * Similar to sendMSHR, but for a write-queue entry
635 * instead. Create the packet, and send it, and if successful also
636 * mark the entry in service.
638 * @param wq_entry The write-queue entry to turn into a packet and send
639 * @return True if the port is waiting for a retry
641 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
643 /** serialize the state of the caches
644 * We currently don't support checkpointing cache state, so this panics.
646 void serialize(CheckpointOut &cp) const override;
647 void unserialize(CheckpointIn &cp) override;
651 * Wrap a method and present it as a cache block visitor.
653 * For example the forEachBlk method in the tag arrays expects a
654 * callable object/function as their parameter. This class wraps a
655 * method in an object and presents callable object that adheres to
656 * the cache block visitor protocol.
658 class CacheBlkVisitorWrapper : public CacheBlkVisitor
661 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
663 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
664 : cache(_cache), visitor(_visitor) {}
666 bool operator()(CacheBlk &blk) override {
667 return (cache.*visitor)(blk);
676 * Cache block visitor that determines if there are dirty blocks in a
679 * Use with the forEachBlk method in the tag array to determine if the
680 * array contains dirty blocks.
682 class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
685 CacheBlkIsDirtyVisitor()
688 bool operator()(CacheBlk &blk) override {
698 * Does the array contain a dirty line?
700 * \return true if yes, false otherwise.
702 bool isDirty() const { return _isDirty; };
708 #endif // __MEM_CACHE_CACHE_HH__