2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Erik Hallnor
49 * Describes a cache based on template policies.
55 #include "base/misc.hh" // fatal, panic, and warn
56 #include "mem/cache/base.hh"
57 #include "mem/cache/blk.hh"
58 #include "mem/cache/mshr.hh"
59 #include "sim/eventq.hh"
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore.
69 template <class TagStore>
70 class Cache : public BaseCache
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
84 class CpuSidePort : public CacheSlavePort
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
93 virtual bool recvTimingSnoop(PacketPtr pkt);
95 virtual bool recvTiming(PacketPtr pkt);
97 virtual Tick recvAtomic(PacketPtr pkt);
99 virtual void recvFunctional(PacketPtr pkt);
101 virtual unsigned deviceBlockSize() const
102 { return cache->getBlockSize(); }
104 virtual AddrRangeList getAddrRanges();
108 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
109 const std::string &_label);
114 * Override the default behaviour of sendDeferredPacket to enable
115 * the memory-side cache port to also send requests based on the
116 * current MSHR status. This queue has a pointer to our specific
117 * cache implementation and is used by the MemSidePort.
119 class MemSidePacketQueue : public PacketQueue
124 Cache<TagStore> &cache;
128 MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
129 const std::string &label) :
130 PacketQueue(cache, port, label), cache(cache) { }
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
137 virtual void sendDeferredPacket();
142 * The memory-side port extends the base cache master port with
143 * access functions for functional, atomic and timing snoops.
145 class MemSidePort : public CacheMasterPort
149 /** The cache-specific queue. */
150 MemSidePacketQueue _queue;
152 // a pointer to our specific cache implementation
153 Cache<TagStore> *cache;
157 virtual bool recvTimingSnoop(PacketPtr pkt);
159 virtual bool recvTiming(PacketPtr pkt);
161 virtual Tick recvAtomicSnoop(PacketPtr pkt);
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
165 virtual unsigned deviceBlockSize() const
166 { return cache->getBlockSize(); }
170 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
171 const std::string &_label);
174 /** Tag and data Storage */
178 BasePrefetcher *prefetcher;
180 /** Temporary cache block for occasional transitory use */
184 * This cache should allocate a block on a line-sized write miss.
186 const bool doFastWrites;
189 * Notify the prefetcher on every access, not just misses.
191 const bool prefetchOnAccess;
194 * Does all the processing necessary to perform the provided request.
195 * @param pkt The memory request to perform.
196 * @param lat The latency of the access.
197 * @param writebacks List for any writebacks that need to be performed.
198 * @param update True if the replacement data should be updated.
199 * @return Boolean indicating whether the request was satisfied.
201 bool access(PacketPtr pkt, BlkType *&blk,
202 int &lat, PacketList &writebacks);
205 *Handle doing the Compare and Swap function for SPARC.
207 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
210 * Find a block frame for new block at address addr, assuming that
211 * the block is not currently in the cache. Append writebacks if
212 * any to provided packet list. Return free block frame. May
213 * return NULL if there are no replaceable blocks at the moment.
215 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
218 * Populates a cache block and handles all outstanding requests for the
219 * satisfied fill request. This version takes two memory requests. One
220 * contains the fill data, the other is an optional target to satisfy.
221 * @param pkt The memory request with the fill data.
222 * @param blk The cache block if it already exists.
223 * @param writebacks List for any writebacks that need to be performed.
224 * @return Pointer to the new cache block.
226 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
227 PacketList &writebacks);
229 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
230 bool deferred_response = false,
231 bool pending_downgrade = false);
232 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
234 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
235 bool already_copied, bool pending_inval);
238 * Sets the blk to the new state.
239 * @param blk The cache block being snooped.
240 * @param new_state The new coherence state for the block.
242 void handleSnoop(PacketPtr ptk, BlkType *blk,
243 bool is_timing, bool is_deferred, bool pending_inval);
246 * Create a writeback request for the given block.
247 * @param blk The block to writeback.
248 * @return The writeback request for the block.
250 PacketPtr writebackBlk(BlkType *blk);
253 /** Instantiates a basic cache object. */
254 Cache(const Params *p, TagStore *tags);
259 * Performs the access specified by the request.
260 * @param pkt The request to perform.
261 * @return The result of the access.
263 bool timingAccess(PacketPtr pkt);
266 * Performs the access specified by the request.
267 * @param pkt The request to perform.
268 * @return The result of the access.
270 Tick atomicAccess(PacketPtr pkt);
273 * Performs the access specified by the request.
274 * @param pkt The request to perform.
275 * @param fromCpuSide from the CPU side port or the memory side port
277 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
280 * Handles a response (cache line fill/write ack) from the bus.
281 * @param pkt The request being responded to.
283 void handleResponse(PacketPtr pkt);
286 * Snoops bus transactions to maintain coherence.
287 * @param pkt The current bus transaction.
289 void snoopTiming(PacketPtr pkt);
292 * Snoop for the provided request in the cache and return the estimated
293 * time of completion.
294 * @param pkt The memory request to snoop
295 * @return The estimated completion time.
297 Tick snoopAtomic(PacketPtr pkt);
300 * Squash all requests associated with specified thread.
301 * intended for use by I-cache.
302 * @param threadNum The thread to squash.
304 void squash(int threadNum);
307 * Generate an appropriate downstream bus request packet for the
309 * @param cpu_pkt The upstream request that needs to be satisfied.
310 * @param blk The block currently in the cache corresponding to
311 * cpu_pkt (NULL if none).
312 * @param needsExclusive Indicates that an exclusive copy is required
313 * even if the request in cpu_pkt doesn't indicate that.
314 * @return A new Packet containing the request, or NULL if the
315 * current request in cpu_pkt should just be forwarded on.
317 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
318 bool needsExclusive);
321 * Return the next MSHR to service, either a pending miss from the
322 * mshrQueue, a buffered write from the write buffer, or something
323 * from the prefetcher. This function is responsible for
324 * prioritizing among those sources on the fly.
329 * Selects an outstanding request to service. Called when the
330 * cache gets granted the downstream bus in timing mode.
331 * @return The request to service, NULL if none found.
333 PacketPtr getTimingPacket();
336 * Marks a request as in service (sent on the bus). This can have side
337 * effect since storage for no response commands is deallocated once they
338 * are successfully sent.
339 * @param pkt The request that was sent on the bus.
341 void markInService(MSHR *mshr, PacketPtr pkt = 0);
344 * Perform the given writeback request.
345 * @param pkt The writeback request.
347 void doWriteback(PacketPtr pkt);
350 * Return whether there are any outstanding misses.
352 bool outstandingMisses() const
354 return mshrQueue.allocated != 0;
357 CacheBlk *findBlock(Addr addr) {
358 return tags->findBlock(addr);
361 bool inCache(Addr addr) {
362 return (tags->findBlock(addr) != 0);
365 bool inMissQueue(Addr addr) {
366 return (mshrQueue.findMatch(addr) != 0);
370 * Find next request ready time from among possible sources.
372 Tick nextMSHRReadyTime();
375 #endif // __CACHE_HH__