2 * Copyright (c) 2012-2018 ARM Limited
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14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Erik Hallnor
52 #ifndef __MEM_CACHE_CACHE_HH__
53 #define __MEM_CACHE_CACHE_HH__
56 #include <unordered_set>
58 #include "base/types.hh"
59 #include "mem/cache/base.hh"
60 #include "mem/packet.hh"
67 * A coherent cache that can be arranged in flexible topologies.
69 class Cache : public BaseCache
73 * This cache should allocate a block on a line-sized write miss.
75 const bool doFastWrites;
78 * Store the outstanding requests that we are expecting snoop
79 * responses from so we can determine which snoop responses we
80 * generated and which ones were merely forwarded.
82 std::unordered_set<RequestPtr> outstandingSnoop;
86 * Turn line-sized writes into WriteInvalidate transactions.
88 void promoteWholeLineWrites(PacketPtr pkt);
90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
91 PacketList &writebacks) override;
93 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
94 Tick request_time) override;
96 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
98 Tick request_time) override;
100 void recvTimingReq(PacketPtr pkt) override;
102 void doWritebacks(PacketList& writebacks, Tick forward_time) override;
104 void doWritebacksAtomic(PacketList& writebacks) override;
106 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
107 PacketList& writebacks) override;
109 void recvTimingSnoopReq(PacketPtr pkt) override;
111 void recvTimingSnoopResp(PacketPtr pkt) override;
113 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
114 PacketList &writebacks) override;
116 Tick recvAtomic(PacketPtr pkt) override;
118 Tick recvAtomicSnoop(PacketPtr pkt) override;
120 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
121 bool deferred_response = false,
122 bool pending_downgrade = false) override;
124 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
125 bool already_copied, bool pending_inval);
128 * Perform an upward snoop if needed, and update the block state
129 * (possibly invalidating the block). Also create a response if required.
131 * @param pkt Snoop packet
132 * @param blk Cache block being snooped
133 * @param is_timing Timing or atomic for the response
134 * @param is_deferred Is this a deferred snoop or not?
135 * @param pending_inval Do we have a pending invalidation?
137 * @return The snoop delay incurred by the upwards snoop
139 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
140 bool is_timing, bool is_deferred, bool pending_inval);
142 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
145 * Create a CleanEvict request for the given block.
147 * @param blk The block to evict.
148 * @return The CleanEvict request for the block.
150 PacketPtr cleanEvictBlk(CacheBlk *blk);
152 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
154 bool is_whole_line_write) const override;
157 * Send up a snoop request and find cached copies. If cached copies are
158 * found, set the BLOCK_CACHED flag in pkt.
160 bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
163 /** Instantiates a basic cache object. */
164 Cache(const CacheParams *p);
167 * Take an MSHR, turn it into a suitable downstream packet, and
168 * send it out. This construct allows a queue entry to choose a suitable
169 * approach based on its type.
171 * @param mshr The MSHR to turn into a packet and send
172 * @return True if the port is waiting for a retry
174 bool sendMSHRQueuePacket(MSHR* mshr) override;
177 #endif // __MEM_CACHE_CACHE_HH__