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40 * Authors: Erik Hallnor
48 * Describes a cache based on template policies.
54 #include "base/misc.hh" // fatal, panic, and warn
55 #include "mem/cache/base.hh"
56 #include "mem/cache/blk.hh"
57 #include "mem/cache/mshr.hh"
58 #include "sim/eventq.hh"
64 * A template-policy based cache. The behavior of the cache can be altered by
65 * supplying different template policies. TagStore handles all tag and data
66 * storage @sa TagStore.
68 template <class TagStore>
69 class Cache : public BaseCache
72 /** Define the type of cache block to use. */
73 typedef typename TagStore::BlkType BlkType;
74 /** A typedef for a list of BlkType pointers. */
75 typedef typename TagStore::BlkList BlkList;
79 class CpuSidePort : public CachePort
82 CpuSidePort(const std::string &_name,
83 Cache<TagStore> *_cache,
84 const std::string &_label);
86 // BaseCache::CachePort just has a BaseCache *; this function
87 // lets us get back the type info we lost when we stored the
88 // cache pointer there.
89 Cache<TagStore> *myCache() {
90 return static_cast<Cache<TagStore> *>(cache);
93 virtual AddrRangeList getAddrRanges();
95 virtual bool recvTiming(PacketPtr pkt);
97 virtual Tick recvAtomic(PacketPtr pkt);
99 virtual void recvFunctional(PacketPtr pkt);
102 class MemSidePort : public CachePort
105 MemSidePort(const std::string &_name,
106 Cache<TagStore> *_cache,
107 const std::string &_label);
109 // BaseCache::CachePort just has a BaseCache *; this function
110 // lets us get back the type info we lost when we stored the
111 // cache pointer there.
112 Cache<TagStore> *myCache() {
113 return static_cast<Cache<TagStore> *>(cache);
118 void processSendEvent();
120 virtual bool isSnooping();
122 virtual bool recvTiming(PacketPtr pkt);
124 virtual void recvRetry();
126 virtual Tick recvAtomic(PacketPtr pkt);
128 virtual void recvFunctional(PacketPtr pkt);
130 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
134 /** Tag and data Storage */
138 BasePrefetcher *prefetcher;
140 /** Temporary cache block for occasional transitory use */
144 * This cache should allocate a block on a line-sized write miss.
146 const bool doFastWrites;
149 * Notify the prefetcher on every access, not just misses.
151 const bool prefetchOnAccess;
154 * Does all the processing necessary to perform the provided request.
155 * @param pkt The memory request to perform.
156 * @param lat The latency of the access.
157 * @param writebacks List for any writebacks that need to be performed.
158 * @param update True if the replacement data should be updated.
159 * @return Boolean indicating whether the request was satisfied.
161 bool access(PacketPtr pkt, BlkType *&blk,
162 int &lat, PacketList &writebacks);
165 *Handle doing the Compare and Swap function for SPARC.
167 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
170 * Find a block frame for new block at address addr, assuming that
171 * the block is not currently in the cache. Append writebacks if
172 * any to provided packet list. Return free block frame. May
173 * return NULL if there are no replaceable blocks at the moment.
175 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
178 * Populates a cache block and handles all outstanding requests for the
179 * satisfied fill request. This version takes two memory requests. One
180 * contains the fill data, the other is an optional target to satisfy.
181 * @param pkt The memory request with the fill data.
182 * @param blk The cache block if it already exists.
183 * @param writebacks List for any writebacks that need to be performed.
184 * @return Pointer to the new cache block.
186 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
187 PacketList &writebacks);
189 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
190 bool deferred_response = false,
191 bool pending_downgrade = false);
192 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
194 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
195 bool already_copied, bool pending_inval);
198 * Sets the blk to the new state.
199 * @param blk The cache block being snooped.
200 * @param new_state The new coherence state for the block.
202 void handleSnoop(PacketPtr ptk, BlkType *blk,
203 bool is_timing, bool is_deferred, bool pending_inval);
206 * Create a writeback request for the given block.
207 * @param blk The block to writeback.
208 * @return The writeback request for the block.
210 PacketPtr writebackBlk(BlkType *blk);
213 /** Instantiates a basic cache object. */
214 Cache(const Params *p, TagStore *tags);
216 virtual Port *getPort(const std::string &if_name, int idx = -1);
221 * Performs the access specified by the request.
222 * @param pkt The request to perform.
223 * @return The result of the access.
225 bool timingAccess(PacketPtr pkt);
228 * Performs the access specified by the request.
229 * @param pkt The request to perform.
230 * @return The result of the access.
232 Tick atomicAccess(PacketPtr pkt);
235 * Performs the access specified by the request.
236 * @param pkt The request to perform.
237 * @param fromCpuSide from the CPU side port or the memory side port
239 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
242 * Handles a response (cache line fill/write ack) from the bus.
243 * @param pkt The request being responded to.
245 void handleResponse(PacketPtr pkt);
248 * Snoops bus transactions to maintain coherence.
249 * @param pkt The current bus transaction.
251 void snoopTiming(PacketPtr pkt);
254 * Snoop for the provided request in the cache and return the estimated
255 * time of completion.
256 * @param pkt The memory request to snoop
257 * @return The estimated completion time.
259 Tick snoopAtomic(PacketPtr pkt);
262 * Squash all requests associated with specified thread.
263 * intended for use by I-cache.
264 * @param threadNum The thread to squash.
266 void squash(int threadNum);
269 * Generate an appropriate downstream bus request packet for the
271 * @param cpu_pkt The upstream request that needs to be satisfied.
272 * @param blk The block currently in the cache corresponding to
273 * cpu_pkt (NULL if none).
274 * @param needsExclusive Indicates that an exclusive copy is required
275 * even if the request in cpu_pkt doesn't indicate that.
276 * @return A new Packet containing the request, or NULL if the
277 * current request in cpu_pkt should just be forwarded on.
279 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
280 bool needsExclusive);
283 * Return the next MSHR to service, either a pending miss from the
284 * mshrQueue, a buffered write from the write buffer, or something
285 * from the prefetcher. This function is responsible for
286 * prioritizing among those sources on the fly.
291 * Selects an outstanding request to service. Called when the
292 * cache gets granted the downstream bus in timing mode.
293 * @return The request to service, NULL if none found.
295 PacketPtr getTimingPacket();
298 * Marks a request as in service (sent on the bus). This can have side
299 * effect since storage for no response commands is deallocated once they
300 * are successfully sent.
301 * @param pkt The request that was sent on the bus.
303 void markInService(MSHR *mshr, PacketPtr pkt = 0);
306 * Perform the given writeback request.
307 * @param pkt The writeback request.
309 void doWriteback(PacketPtr pkt);
312 * Return whether there are any outstanding misses.
314 bool outstandingMisses() const
316 return mshrQueue.allocated != 0;
319 CacheBlk *findBlock(Addr addr) {
320 return tags->findBlock(addr);
323 bool inCache(Addr addr) {
324 return (tags->findBlock(addr) != 0);
327 bool inMissQueue(Addr addr) {
328 return (mshrQueue.findMatch(addr) != 0);
332 * Find next request ready time from among possible sources.
334 Tick nextMSHRReadyTime();
337 #endif // __CACHE_HH__