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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/misc.hh" // fatal, panic, and warn
44 #include "mem/cache/base_cache.hh"
45 #include "mem/cache/cache_blk.hh"
46 #include "mem/cache/miss/mshr.hh"
48 #include "sim/eventq.hh"
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
58 template <class TagStore>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
71 class CpuSidePort : public CachePort
74 CpuSidePort(const std::string &_name,
75 Cache<TagStore> *_cache,
76 std::vector<Range<Addr> > filterRanges);
78 // BaseCache::CachePort just has a BaseCache *; this function
79 // lets us get back the type info we lost when we stored the
80 // cache pointer there.
81 Cache<TagStore> *myCache() {
82 return static_cast<Cache<TagStore> *>(cache);
85 virtual void getDeviceAddressRanges(AddrRangeList &resp,
88 virtual bool recvTiming(PacketPtr pkt);
90 virtual Tick recvAtomic(PacketPtr pkt);
92 virtual void recvFunctional(PacketPtr pkt);
95 class MemSidePort : public CachePort
98 MemSidePort(const std::string &_name,
99 Cache<TagStore> *_cache,
100 std::vector<Range<Addr> > filterRanges);
102 // BaseCache::CachePort just has a BaseCache *; this function
103 // lets us get back the type info we lost when we stored the
104 // cache pointer there.
105 Cache<TagStore> *myCache() {
106 return static_cast<Cache<TagStore> *>(cache);
111 void processSendEvent();
113 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 virtual bool recvTiming(PacketPtr pkt);
118 virtual void recvRetry();
120 virtual Tick recvAtomic(PacketPtr pkt);
122 virtual void recvFunctional(PacketPtr pkt);
124 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
128 /** Tag and data Storage */
132 BasePrefetcher *prefetcher;
134 /** Temporary cache block for occasional transitory use */
138 * Can this cache should allocate a block on a line-sized write miss.
140 const bool doFastWrites;
142 const bool prefetchMiss;
145 * Handle a replacement for the given request.
146 * @param blk A pointer to the block, usually NULL
147 * @param pkt The memory request to satisfy.
148 * @param new_state The new state of the block.
149 * @param writebacks A list to store any generated writebacks.
151 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
152 CacheBlk::State new_state, PacketList &writebacks);
155 * Does all the processing necessary to perform the provided request.
156 * @param pkt The memory request to perform.
157 * @param lat The latency of the access.
158 * @param writebacks List for any writebacks that need to be performed.
159 * @param update True if the replacement data should be updated.
160 * @return Pointer to the cache block touched by the request. NULL if it
163 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
166 *Handle doing the Compare and Swap function for SPARC.
168 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
171 * Populates a cache block and handles all outstanding requests for the
172 * satisfied fill request. This version takes two memory requests. One
173 * contains the fill data, the other is an optional target to satisfy.
174 * Used for Cache::probe.
175 * @param pkt The memory request with the fill data.
176 * @param blk The cache block if it already exists.
177 * @param writebacks List for any writebacks that need to be performed.
178 * @return Pointer to the new cache block.
180 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
181 PacketList &writebacks);
183 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
184 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
186 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
187 bool already_copied);
190 * Sets the blk to the new state.
191 * @param blk The cache block being snooped.
192 * @param new_state The new coherence state for the block.
194 void handleSnoop(PacketPtr ptk, BlkType *blk,
195 bool is_timing, bool is_deferred);
198 * Create a writeback request for the given block.
199 * @param blk The block to writeback.
200 * @return The writeback request for the block.
202 PacketPtr writebackBlk(BlkType *blk);
210 BaseCache::Params baseParams;
211 BasePrefetcher*prefetcher;
213 const bool doFastWrites;
214 const bool prefetchMiss;
216 Params(TagStore *_tags,
217 BaseCache::Params params,
218 BasePrefetcher *_prefetcher,
219 bool prefetch_access, int hit_latency,
224 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
225 doFastWrites(do_fast_writes),
226 prefetchMiss(prefetch_miss)
231 /** Instantiates a basic cache object. */
232 Cache(const std::string &_name, Params ¶ms);
234 virtual Port *getPort(const std::string &if_name, int idx = -1);
235 virtual void deletePortRefs(Port *p);
240 * Performs the access specified by the request.
241 * @param pkt The request to perform.
242 * @return The result of the access.
244 bool timingAccess(PacketPtr pkt);
247 * Performs the access specified by the request.
248 * @param pkt The request to perform.
249 * @return The result of the access.
251 Tick atomicAccess(PacketPtr pkt);
254 * Performs the access specified by the request.
255 * @param pkt The request to perform.
256 * @return The result of the access.
258 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
261 * Handles a response (cache line fill/write ack) from the bus.
262 * @param pkt The request being responded to.
264 void handleResponse(PacketPtr pkt);
267 * Snoops bus transactions to maintain coherence.
268 * @param pkt The current bus transaction.
270 void snoopTiming(PacketPtr pkt);
273 * Snoop for the provided request in the cache and return the estimated
274 * time of completion.
275 * @param pkt The memory request to snoop
276 * @return The estimated completion time.
278 Tick snoopAtomic(PacketPtr pkt);
281 * Squash all requests associated with specified thread.
282 * intended for use by I-cache.
283 * @param threadNum The thread to squash.
285 void squash(int threadNum);
288 * Selects a outstanding request to service.
289 * @return The request to service, NULL if none found.
291 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
292 bool needsExclusive);
294 PacketPtr getTimingPacket();
297 * Marks a request as in service (sent on the bus). This can have side
298 * effect since storage for no response commands is deallocated once they
299 * are successfully sent.
300 * @param pkt The request that was sent on the bus.
302 void markInService(MSHR *mshr);
305 * Perform the given writeback request.
306 * @param pkt The writeback request.
308 void doWriteback(PacketPtr pkt);
311 * Return whether there are any outstanding misses.
313 bool outstandingMisses() const
315 return mshrQueue.allocated != 0;
318 CacheBlk *findBlock(Addr addr) {
319 return tags->findBlock(addr);
322 bool inCache(Addr addr) {
323 return (tags->findBlock(addr) != 0);
326 bool inMissQueue(Addr addr) {
327 return (mshrQueue.findMatch(addr) != 0);
331 #endif // __CACHE_HH__