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28 * Authors: Erik Hallnor
35 * Describes a cache based on template policies.
41 #include "base/misc.hh" // fatal, panic, and warn
42 #include "cpu/smt.hh" // SMT_MAX_THREADS
44 #include "mem/cache/base_cache.hh"
45 #include "mem/cache/prefetch/prefetcher.hh"
47 // forward declarations
51 * A template-policy based cache. The behavior of the cache can be altered by
52 * supplying different template policies. TagStore handles all tag and data
53 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
54 * @sa MissQueue. Coherence handles all coherence policy details @sa
55 * UniCoherence, SimpleMultiCoherence.
57 template <class TagStore, class Buffering, class Coherence>
58 class Cache : public BaseCache
61 /** Define the type of cache block to use. */
62 typedef typename TagStore::BlkType BlkType;
67 /** Tag and data Storage */
69 /** Miss and Writeback handler */
71 /** Coherence protocol. */
75 Prefetcher<TagStore, Buffering> *prefetcher;
77 /** Do fast copies in this cache. */
80 /** Block on a delayed copy. */
84 * The clock ratio of the outgoing bus.
85 * Used for calculating critical word first.
90 * The bus width in bytes of the outgoing bus.
91 * Used for calculating critical word first.
96 * A permanent mem req to always be used to cause invalidations.
97 * Used to append to target list, to cause an invalidation.
99 Packet * invalidatePkt;
102 * Temporarily move a block into a MSHR.
103 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
105 void pseudoFill(Addr addr, int asid);
108 * Temporarily move a block into an existing MSHR.
109 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
111 void pseudoFill(MSHR *mshr);
119 Buffering *missQueue;
120 Coherence *coherence;
123 BaseCache::Params baseParams;
126 Prefetcher<TagStore, Buffering> *prefetcher;
129 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
130 bool do_copy, BaseCache::Params params, Bus * in_bus,
131 Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
132 bool prefetch_access)
133 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
134 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
135 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
140 /** Instantiates a basic cache object. */
141 Cache(const std::string &_name, Params ¶ms);
146 * Performs the access specified by the request.
147 * @param req The request to perform.
148 * @return The result of the access.
150 bool access(Packet * &pkt);
153 * Selects a request to send on the bus.
154 * @return The memory request to service.
156 Packet * getPacket();
159 * Was the request was sent successfully?
160 * @param req The request.
161 * @param success True if the request was sent successfully.
163 void sendResult(Packet * &pkt, bool success);
166 * Handles a response (cache line fill/write ack) from the bus.
167 * @param req The request being responded to.
169 void handleResponse(Packet * &pkt);
172 * Start handling a copy transaction.
173 * @param req The copy request to perform.
175 void startCopy(Packet * &pkt);
178 * Handle a delayed copy transaction.
179 * @param req The delayed copy request to continue.
180 * @param addr The address being responded to.
181 * @param blk The block of the current response.
182 * @param mshr The mshr being handled.
184 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
187 * Selects a coherence message to forward to lower levels of the hierarchy.
188 * @return The coherence message to forward.
190 Packet * getCoherenceReq();
193 * Snoops bus transactions to maintain coherence.
194 * @param req The current bus transaction.
196 void snoop(Packet * &pkt);
198 void snoopResponse(Packet * &pkt);
201 * Invalidates the block containing address if found.
202 * @param addr The address to look for.
203 * @param asid The address space ID of the address.
204 * @todo Is this function necessary?
206 void invalidateBlk(Addr addr, int asid);
209 * Aquash all requests associated with specified thread.
210 * intended for use by I-cache.
211 * @param req->getThreadNum()ber The thread to squash.
213 void squash(int threadNum)
215 missQueue->squash(threadNum);
219 * Return the number of outstanding misses in a Cache.
222 * @retval unsigned The number of missing still outstanding.
224 unsigned outstandingMisses() const
226 return missQueue->getMisses();
230 * Send a response to the slave interface.
231 * @param req The request being responded to.
232 * @param time The time the response is ready.
234 void respond(Packet * &pkt, Tick time)
236 //si->respond(pkt,time);
237 cpuSidePort->sendAtomic(pkt);
241 * Perform the access specified in the request and return the estimated
242 * time of completion. This function can either update the hierarchy state
243 * or just perform the access wherever the data is found depending on the
244 * state of the update flag.
245 * @param req The memory request to satisfy
246 * @param update If true, update the hierarchy, otherwise just perform the
248 * @return The estimated completion time.
250 Tick probe(Packet * &pkt, bool update);
253 * Snoop for the provided request in the cache and return the estimated
254 * time of completion.
255 * @todo Can a snoop probe not change state?
256 * @param req The memory request to satisfy
257 * @param update If true, update the hierarchy, otherwise just perform the
259 * @return The estimated completion time.
261 Tick snoopProbe(Packet * &pkt, bool update);
264 #endif // __CACHE_HH__