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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/compression/base.hh"
43 #include "base/misc.hh" // fatal, panic, and warn
44 #include "cpu/smt.hh" // SMT_MAX_THREADS
46 #include "mem/cache/base_cache.hh"
47 #include "mem/cache/cache_blk.hh"
48 #include "mem/cache/miss/mshr.hh"
50 #include "sim/eventq.hh"
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
62 template <class TagStore, class Coherence>
63 class Cache : public BaseCache
66 /** Define the type of cache block to use. */
67 typedef typename TagStore::BlkType BlkType;
68 /** A typedef for a list of BlkType pointers. */
69 typedef typename TagStore::BlkList BlkList;
75 class CpuSidePort : public CachePort
78 CpuSidePort(const std::string &_name,
79 Cache<TagStore,Coherence> *_cache);
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
91 virtual bool recvTiming(PacketPtr pkt);
93 virtual Tick recvAtomic(PacketPtr pkt);
95 virtual void recvFunctional(PacketPtr pkt);
98 class MemSidePort : public CachePort
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
113 void processSendEvent();
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
118 virtual bool recvTiming(PacketPtr pkt);
120 virtual void recvRetry();
122 virtual Tick recvAtomic(PacketPtr pkt);
124 virtual void recvFunctional(PacketPtr pkt);
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
130 /** Tag and data Storage */
133 /** Coherence protocol. */
134 Coherence *coherence;
137 BasePrefetcher *prefetcher;
140 * Can this cache should allocate a block on a line-sized write miss.
142 const bool doFastWrites;
144 const bool prefetchMiss;
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
165 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
168 *Handle doing the Compare and Swap function for SPARC.
170 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
173 * Populates a cache block and handles all outstanding requests for the
174 * satisfied fill request. This version takes two memory requests. One
175 * contains the fill data, the other is an optional target to satisfy.
176 * Used for Cache::probe.
177 * @param pkt The memory request with the fill data.
178 * @param blk The cache block if it already exists.
179 * @param writebacks List for any writebacks that need to be performed.
180 * @return Pointer to the new cache block.
182 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
183 PacketList &writebacks);
185 bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
186 bool satisfyTarget(MSHR::Target *target, BlkType *blk);
187 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
189 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data);
192 * Sets the blk to the new state.
193 * @param blk The cache block being snooped.
194 * @param new_state The new coherence state for the block.
196 void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing);
199 * Create a writeback request for the given block.
200 * @param blk The block to writeback.
201 * @return The writeback request for the block.
203 PacketPtr writebackBlk(BlkType *blk);
211 Coherence *coherence;
212 BaseCache::Params baseParams;
213 BasePrefetcher*prefetcher;
215 const bool doFastWrites;
216 const bool prefetchMiss;
218 Params(TagStore *_tags, Coherence *coh,
219 BaseCache::Params params,
220 BasePrefetcher *_prefetcher,
221 bool prefetch_access, int hit_latency,
224 : tags(_tags), coherence(coh),
226 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
227 doFastWrites(do_fast_writes),
228 prefetchMiss(prefetch_miss)
233 /** Instantiates a basic cache object. */
234 Cache(const std::string &_name, Params ¶ms);
236 virtual Port *getPort(const std::string &if_name, int idx = -1);
237 virtual void deletePortRefs(Port *p);
242 * Performs the access specified by the request.
243 * @param pkt The request to perform.
244 * @return The result of the access.
246 bool timingAccess(PacketPtr pkt);
249 * Performs the access specified by the request.
250 * @param pkt The request to perform.
251 * @return The result of the access.
253 Tick atomicAccess(PacketPtr pkt);
256 * Performs the access specified by the request.
257 * @param pkt The request to perform.
258 * @return The result of the access.
260 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
263 * Handles a response (cache line fill/write ack) from the bus.
264 * @param pkt The request being responded to.
266 void handleResponse(PacketPtr pkt);
269 * Snoops bus transactions to maintain coherence.
270 * @param pkt The current bus transaction.
272 void snoopTiming(PacketPtr pkt);
275 * Snoop for the provided request in the cache and return the estimated
276 * time of completion.
277 * @param pkt The memory request to snoop
278 * @return The estimated completion time.
280 Tick snoopAtomic(PacketPtr pkt);
283 * Squash all requests associated with specified thread.
284 * intended for use by I-cache.
285 * @param threadNum The thread to squash.
287 void squash(int threadNum);
290 * Selects a outstanding request to service.
291 * @return The request to service, NULL if none found.
293 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
294 bool needsExclusive);
296 PacketPtr getTimingPacket();
299 * Marks a request as in service (sent on the bus). This can have side
300 * effect since storage for no response commands is deallocated once they
301 * are successfully sent.
302 * @param pkt The request that was sent on the bus.
304 void markInService(MSHR *mshr);
307 * Perform the given writeback request.
308 * @param pkt The writeback request.
310 void doWriteback(PacketPtr pkt);
313 * Return whether there are any outstanding misses.
315 bool outstandingMisses() const
317 return mshrQueue.allocated != 0;
320 CacheBlk *findBlock(Addr addr) {
321 return tags->findBlock(addr);
324 bool inCache(Addr addr) {
325 return (tags->findBlock(addr) != 0);
328 bool inMissQueue(Addr addr) {
329 return (mshrQueue.findMatch(addr) != 0);
333 #endif // __CACHE_HH__