src/mem/cache/cache.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Steve Reinhardt
  31  */
  32
  33 /**
  34  * @file
  35  * Describes a cache based on template policies.
  36  */
  37
  38 #ifndef __CACHE_HH__
  39 #define __CACHE_HH__
  40
  41 #include "base/compression/base.hh"
  42 #include "base/misc.hh" // fatal, panic, and warn
  43 #include "cpu/smt.hh" // SMT_MAX_THREADS
  44
  45 #include "mem/cache/base_cache.hh"
  46 #include "mem/cache/cache_blk.hh"
  47 #include "mem/cache/miss/miss_buffer.hh"
  48
  49 //Forward decleration
  50 class MSHR;
  51 class BasePrefetcher;
  52
  53 /**
  54  * A template-policy based cache. The behavior of the cache can be altered by
  55  * supplying different template policies. TagStore handles all tag and data
  56  * storage @sa TagStore. Buffering handles all misses and writes/writebacks
  57  * @sa MissQueue. Coherence handles all coherence policy details @sa
  58  * UniCoherence, SimpleMultiCoherence.
  59  */
  60 template <class TagStore, class Coherence>
  61 class Cache : public BaseCache
  62 {
  63   public:
  64     /** Define the type of cache block to use. */
  65     typedef typename TagStore::BlkType BlkType;
  66     /** A typedef for a list of BlkType pointers. */
  67     typedef typename TagStore::BlkList BlkList;
  68
  69     bool prefetchAccess;
  70
  71   protected:
  72
  73     class CpuSidePort : public CachePort
  74     {
  75       public:
  76         CpuSidePort(const std::string &_name,
  77                     Cache<TagStore,Coherence> *_cache);
  78
  79         // BaseCache::CachePort just has a BaseCache *; this function
  80         // lets us get back the type info we lost when we stored the
  81         // cache pointer there.
  82         Cache<TagStore,Coherence> *myCache() {
  83             return static_cast<Cache<TagStore,Coherence> *>(cache);
  84         }
  85
  86         virtual bool recvTiming(PacketPtr pkt);
  87
  88         virtual Tick recvAtomic(PacketPtr pkt);
  89
  90         virtual void recvFunctional(PacketPtr pkt);
  91     };
  92
  93     class MemSidePort : public CachePort
  94     {
  95       public:
  96         MemSidePort(const std::string &_name,
  97                     Cache<TagStore,Coherence> *_cache);
  98
  99         // BaseCache::CachePort just has a BaseCache *; this function
 100         // lets us get back the type info we lost when we stored the
 101         // cache pointer there.
 102         Cache<TagStore,Coherence> *myCache() {
 103             return static_cast<Cache<TagStore,Coherence> *>(cache);
 104         }
 105
 106         virtual bool recvTiming(PacketPtr pkt);
 107
 108         virtual Tick recvAtomic(PacketPtr pkt);
 109
 110         virtual void recvFunctional(PacketPtr pkt);
 111     };
 112
 113     /** Tag and data Storage */
 114     TagStore *tags;
 115     /** Miss and Writeback handler */
 116     MissBuffer *missQueue;
 117     /** Coherence protocol. */
 118     Coherence *coherence;
 119
 120     /** Prefetcher */
 121     BasePrefetcher *prefetcher;
 122
 123     /**
 124      * The clock ratio of the outgoing bus.
 125      * Used for calculating critical word first.
 126      */
 127     int busRatio;
 128
 129      /**
 130       * The bus width in bytes of the outgoing bus.
 131       * Used for calculating critical word first.
 132       */
 133     int busWidth;
 134
 135     /**
 136      * The latency of a hit in this device.
 137      */
 138     int hitLatency;
 139
 140      /**
 141       * A permanent mem req to always be used to cause invalidations.
 142       * Used to append to target list, to cause an invalidation.
 143       */
 144     PacketPtr invalidatePkt;
 145     Request *invalidateReq;
 146
 147     /**
 148      * Policy class for performing compression.
 149      */
 150     CompressionAlgorithm *compressionAlg;
 151
 152     /**
 153      * The block size of this cache. Set to value in the Tags object.
 154      */
 155     const int16_t blkSize;
 156
 157     /**
 158      * Can this cache should allocate a block on a line-sized write miss.
 159      */
 160     const bool doFastWrites;
 161
 162     const bool prefetchMiss;
 163
 164     /**
 165      * Can the data can be stored in a compressed form.
 166      */
 167     const bool storeCompressed;
 168
 169     /**
 170      * Do we need to compress blocks on writebacks (i.e. because
 171      * writeback bus is compressed but storage is not)?
 172      */
 173     const bool compressOnWriteback;
 174
 175     /**
 176      * The latency of a compression operation.
 177      */
 178     const int16_t compLatency;
 179
 180     /**
 181      * Should we use an adaptive compression scheme.
 182      */
 183     const bool adaptiveCompression;
 184
 185     /**
 186      * Do writebacks need to be compressed (i.e. because writeback bus
 187      * is compressed), whether or not they're already compressed for
 188      * storage.
 189      */
 190     const bool writebackCompressed;
 191
 192     /**
 193      * Compare the internal block data to the fast access block data.
 194      * @param blk The cache block to check.
 195      * @return True if the data is the same.
 196      */
 197     bool verifyData(BlkType *blk);
 198
 199     /**
 200      * Update the internal data of the block. The data to write is assumed to
 201      * be in the fast access data.
 202      * @param blk The block with the data to update.
 203      * @param writebacks A list to store any generated writebacks.
 204      * @param compress_block True if we should compress this block
 205      */
 206     void updateData(BlkType *blk, PacketList &writebacks, bool compress_block);
 207
 208     /**
 209      * Handle a replacement for the given request.
 210      * @param blk A pointer to the block, usually NULL
 211      * @param pkt The memory request to satisfy.
 212      * @param new_state The new state of the block.
 213      * @param writebacks A list to store any generated writebacks.
 214      */
 215     BlkType* doReplacement(BlkType *blk, PacketPtr &pkt,
 216                            CacheBlk::State new_state, PacketList &writebacks);
 217
 218     /**
 219      * Does all the processing necessary to perform the provided request.
 220      * @param pkt The memory request to perform.
 221      * @param lat The latency of the access.
 222      * @param writebacks List for any writebacks that need to be performed.
 223      * @param update True if the replacement data should be updated.
 224      * @return Pointer to the cache block touched by the request. NULL if it
 225      * was a miss.
 226      */
 227     BlkType* handleAccess(PacketPtr &pkt, int & lat,
 228                           PacketList & writebacks, bool update = true);
 229
 230
 231     /**
 232      *Handle doing the Compare and Swap function for SPARC.
 233      */
 234     void cmpAndSwap(BlkType *blk, PacketPtr &pkt);
 235
 236     /**
 237      * Populates a cache block and handles all outstanding requests for the
 238      * satisfied fill request. This version takes an MSHR pointer and uses its
 239      * request to fill the cache block, while repsonding to its targets.
 240      * @param blk The cache block if it already exists.
 241      * @param mshr The MSHR that contains the fill data and targets to satisfy.
 242      * @param new_state The state of the new cache block.
 243      * @param writebacks List for any writebacks that need to be performed.
 244      * @return Pointer to the new cache block.
 245      */
 246     BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state,
 247                         PacketList & writebacks, PacketPtr pkt);
 248
 249     /**
 250      * Populates a cache block and handles all outstanding requests for the
 251      * satisfied fill request. This version takes two memory requests. One
 252      * contains the fill data, the other is an optional target to satisfy.
 253      * Used for Cache::probe.
 254      * @param blk The cache block if it already exists.
 255      * @param pkt The memory request with the fill data.
 256      * @param new_state The state of the new cache block.
 257      * @param writebacks List for any writebacks that need to be performed.
 258      * @param target The memory request to perform after the fill.
 259      * @return Pointer to the new cache block.
 260      */
 261     BlkType* handleFill(BlkType *blk, PacketPtr &pkt,
 262                         CacheBlk::State new_state,
 263                         PacketList & writebacks, PacketPtr target = NULL);
 264
 265     /**
 266      * Sets the blk to the new state and handles the given request.
 267      * @param blk The cache block being snooped.
 268      * @param new_state The new coherence state for the block.
 269      * @param pkt The request to satisfy
 270      */
 271     void handleSnoop(BlkType *blk, CacheBlk::State new_state,
 272                      PacketPtr &pkt);
 273
 274     /**
 275      * Sets the blk to the new state.
 276      * @param blk The cache block being snooped.
 277      * @param new_state The new coherence state for the block.
 278      */
 279     void handleSnoop(BlkType *blk, CacheBlk::State new_state);
 280
 281     /**
 282      * Create a writeback request for the given block.
 283      * @param blk The block to writeback.
 284      * @return The writeback request for the block.
 285      */
 286     PacketPtr writebackBlk(BlkType *blk);
 287
 288   public:
 289
 290     class Params
 291     {
 292       public:
 293         TagStore *tags;
 294         MissBuffer *missQueue;
 295         Coherence *coherence;
 296         BaseCache::Params baseParams;
 297         BasePrefetcher*prefetcher;
 298         bool prefetchAccess;
 299         int hitLatency;
 300         CompressionAlgorithm *compressionAlg;
 301         const int16_t blkSize;
 302         const bool doFastWrites;
 303         const bool prefetchMiss;
 304         const bool storeCompressed;
 305         const bool compressOnWriteback;
 306         const int16_t compLatency;
 307         const bool adaptiveCompression;
 308         const bool writebackCompressed;
 309
 310         Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
 311                BaseCache::Params params,
 312                BasePrefetcher *_prefetcher,
 313                bool prefetch_access, int hit_latency,
 314                bool do_fast_writes,
 315                bool store_compressed, bool adaptive_compression,
 316                bool writeback_compressed,
 317                CompressionAlgorithm *_compressionAlg, int comp_latency,
 318                bool prefetch_miss)
 319             : tags(_tags), missQueue(mq), coherence(coh),
 320               baseParams(params),
 321               prefetcher(_prefetcher), prefetchAccess(prefetch_access),
 322               hitLatency(hit_latency),
 323               compressionAlg(_compressionAlg),
 324               blkSize(_tags->getBlockSize()),
 325               doFastWrites(do_fast_writes),
 326               prefetchMiss(prefetch_miss),
 327               storeCompressed(store_compressed),
 328               compressOnWriteback(!store_compressed && writeback_compressed),
 329               compLatency(comp_latency),
 330               adaptiveCompression(adaptive_compression),
 331               writebackCompressed(writeback_compressed)
 332         {
 333         }
 334     };
 335
 336     /** Instantiates a basic cache object. */
 337     Cache(const std::string &_name, Params &params);
 338
 339     virtual Port *getPort(const std::string &if_name, int idx = -1);
 340     virtual void deletePortRefs(Port *p);
 341
 342     virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 343
 344     void regStats();
 345
 346     /**
 347      * Performs the access specified by the request.
 348      * @param pkt The request to perform.
 349      * @return The result of the access.
 350      */
 351     bool access(PacketPtr &pkt);
 352
 353     /**
 354      * Selects a request to send on the bus.
 355      * @return The memory request to service.
 356      */
 357     virtual PacketPtr getPacket();
 358
 359     /**
 360      * Was the request was sent successfully?
 361      * @param pkt The request.
 362      * @param success True if the request was sent successfully.
 363      */
 364     virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
 365
 366     /**
 367      * Was the CSHR request was sent successfully?
 368      * @param pkt The request.
 369      * @param success True if the request was sent successfully.
 370      */
 371     virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
 372
 373     /**
 374      * Handles a response (cache line fill/write ack) from the bus.
 375      * @param pkt The request being responded to.
 376      */
 377     void handleResponse(PacketPtr &pkt);
 378
 379     /**
 380      * Selects a coherence message to forward to lower levels of the hierarchy.
 381      * @return The coherence message to forward.
 382      */
 383     virtual PacketPtr getCoherencePacket();
 384
 385     /**
 386      * Snoops bus transactions to maintain coherence.
 387      * @param pkt The current bus transaction.
 388      */
 389     void snoop(PacketPtr &pkt);
 390
 391     void snoopResponse(PacketPtr &pkt);
 392
 393     /**
 394      * Squash all requests associated with specified thread.
 395      * intended for use by I-cache.
 396      * @param threadNum The thread to squash.
 397      */
 398     void squash(int threadNum)
 399     {
 400         missQueue->squash(threadNum);
 401     }
 402
 403     /**
 404      * Return the number of outstanding misses in a Cache.
 405      * Default returns 0.
 406      *
 407      * @retval unsigned The number of missing still outstanding.
 408      */
 409     unsigned outstandingMisses() const
 410     {
 411         return missQueue->getMisses();
 412     }
 413
 414     /**
 415      * Perform the access specified in the request and return the estimated
 416      * time of completion. This function can either update the hierarchy state
 417      * or just perform the access wherever the data is found depending on the
 418      * state of the update flag.
 419      * @param pkt The memory request to satisfy
 420      * @param update If true, update the hierarchy, otherwise just perform the
 421      * request.
 422      * @return The estimated completion time.
 423      */
 424     Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
 425
 426     /**
 427      * Snoop for the provided request in the cache and return the estimated
 428      * time of completion.
 429      * @todo Can a snoop probe not change state?
 430      * @param pkt The memory request to satisfy
 431      * @param update If true, update the hierarchy, otherwise just perform the
 432      * request.
 433      * @return The estimated completion time.
 434      */
 435     Tick snoopProbe(PacketPtr &pkt);
 436
 437     bool inCache(Addr addr) {
 438         return (tags->findBlock(addr) != 0);
 439     }
 440
 441     bool inMissQueue(Addr addr) {
 442         return (missQueue->findMSHR(addr) != 0);
 443     }
 444 };
 445
 446 #endif // __CACHE_HH__