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28 * Authors: Erik Hallnor
35 * Describes a cache based on template policies.
41 #include "base/misc.hh" // fatal, panic, and warn
42 #include "cpu/smt.hh" // SMT_MAX_THREADS
44 #include "mem/cache/base_cache.hh"
45 #include "mem/cache/prefetch/prefetcher.hh"
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
58 template <class TagStore, class Buffering, class Coherence>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
68 /** Tag and data Storage */
70 /** Miss and Writeback handler */
72 /** Coherence protocol. */
76 Prefetcher<TagStore, Buffering> *prefetcher;
78 /** Do fast copies in this cache. */
81 /** Block on a delayed copy. */
85 * The clock ratio of the outgoing bus.
86 * Used for calculating critical word first.
91 * The bus width in bytes of the outgoing bus.
92 * Used for calculating critical word first.
97 * The latency of a hit in this device.
102 * A permanent mem req to always be used to cause invalidations.
103 * Used to append to target list, to cause an invalidation.
105 Packet * invalidatePkt;
106 Request *invalidateReq;
109 * Temporarily move a block into a MSHR.
110 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
112 void pseudoFill(Addr addr);
115 * Temporarily move a block into an existing MSHR.
116 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
118 void pseudoFill(MSHR *mshr);
126 Buffering *missQueue;
127 Coherence *coherence;
130 BaseCache::Params baseParams;
131 Prefetcher<TagStore, Buffering> *prefetcher;
135 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
136 bool do_copy, BaseCache::Params params,
137 Prefetcher<TagStore, Buffering> *_prefetcher,
138 bool prefetch_access, int hit_latency)
139 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
140 blockOnCopy(false), baseParams(params),
141 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
142 hitLatency(hit_latency)
147 /** Instantiates a basic cache object. */
148 Cache(const std::string &_name, Params ¶ms);
150 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
153 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
155 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
157 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
162 * Performs the access specified by the request.
163 * @param pkt The request to perform.
164 * @return The result of the access.
166 bool access(Packet * &pkt);
169 * Selects a request to send on the bus.
170 * @return The memory request to service.
172 virtual Packet * getPacket();
175 * Was the request was sent successfully?
176 * @param pkt The request.
177 * @param success True if the request was sent successfully.
179 virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
182 * Was the CSHR request was sent successfully?
183 * @param pkt The request.
184 * @param success True if the request was sent successfully.
186 virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
189 * Handles a response (cache line fill/write ack) from the bus.
190 * @param pkt The request being responded to.
192 void handleResponse(Packet * &pkt);
195 * Start handling a copy transaction.
196 * @param pkt The copy request to perform.
198 void startCopy(Packet * &pkt);
201 * Handle a delayed copy transaction.
202 * @param pkt The delayed copy request to continue.
203 * @param addr The address being responded to.
204 * @param blk The block of the current response.
205 * @param mshr The mshr being handled.
207 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
210 * Selects a coherence message to forward to lower levels of the hierarchy.
211 * @return The coherence message to forward.
213 virtual Packet * getCoherencePacket();
216 * Snoops bus transactions to maintain coherence.
217 * @param pkt The current bus transaction.
219 void snoop(Packet * &pkt);
221 void snoopResponse(Packet * &pkt);
224 * Invalidates the block containing address if found.
225 * @param addr The address to look for.
226 * @param asid The address space ID of the address.
227 * @todo Is this function necessary?
229 void invalidateBlk(Addr addr);
232 * Squash all requests associated with specified thread.
233 * intended for use by I-cache.
234 * @param threadNum The thread to squash.
236 void squash(int threadNum)
238 missQueue->squash(threadNum);
242 * Return the number of outstanding misses in a Cache.
245 * @retval unsigned The number of missing still outstanding.
247 unsigned outstandingMisses() const
249 return missQueue->getMisses();
253 * Perform the access specified in the request and return the estimated
254 * time of completion. This function can either update the hierarchy state
255 * or just perform the access wherever the data is found depending on the
256 * state of the update flag.
257 * @param pkt The memory request to satisfy
258 * @param update If true, update the hierarchy, otherwise just perform the
260 * @return The estimated completion time.
262 Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
265 * Snoop for the provided request in the cache and return the estimated
266 * time of completion.
267 * @todo Can a snoop probe not change state?
268 * @param pkt The memory request to satisfy
269 * @param update If true, update the hierarchy, otherwise just perform the
271 * @return The estimated completion time.
273 Tick snoopProbe(Packet * &pkt);
276 #endif // __CACHE_HH__