src/mem/cache/cache.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Steve Reinhardt
  31  */
  32
  33 /**
  34  * @file
  35  * Describes a cache based on template policies.
  36  */
  37
  38 #ifndef __CACHE_HH__
  39 #define __CACHE_HH__
  40
  41 #include "base/misc.hh" // fatal, panic, and warn
  42 #include "cpu/smt.hh" // SMT_MAX_THREADS
  43
  44 #include "mem/cache/base_cache.hh"
  45 #include "mem/cache/prefetch/prefetcher.hh"
  46
  47 //Forward decleration
  48 class MSHR;
  49
  50
  51 /**
  52  * A template-policy based cache. The behavior of the cache can be altered by
  53  * supplying different template policies. TagStore handles all tag and data
  54  * storage @sa TagStore. Buffering handles all misses and writes/writebacks
  55  * @sa MissQueue. Coherence handles all coherence policy details @sa
  56  * UniCoherence, SimpleMultiCoherence.
  57  */
  58 template <class TagStore, class Buffering, class Coherence>
  59 class Cache : public BaseCache
  60 {
  61   public:
  62     /** Define the type of cache block to use. */
  63     typedef typename TagStore::BlkType BlkType;
  64
  65     bool prefetchAccess;
  66   protected:
  67
  68     /** Tag and data Storage */
  69     TagStore *tags;
  70     /** Miss and Writeback handler */
  71     Buffering *missQueue;
  72     /** Coherence protocol. */
  73     Coherence *coherence;
  74
  75     /** Prefetcher */
  76     Prefetcher<TagStore, Buffering> *prefetcher;
  77
  78     /**
  79      * The clock ratio of the outgoing bus.
  80      * Used for calculating critical word first.
  81      */
  82     int busRatio;
  83
  84      /**
  85       * The bus width in bytes of the outgoing bus.
  86       * Used for calculating critical word first.
  87       */
  88     int busWidth;
  89
  90     /**
  91      * The latency of a hit in this device.
  92      */
  93     int hitLatency;
  94
  95      /**
  96       * A permanent mem req to always be used to cause invalidations.
  97       * Used to append to target list, to cause an invalidation.
  98       */
  99     Packet * invalidatePkt;
 100     Request *invalidateReq;
 101
 102   public:
 103
 104     class Params
 105     {
 106       public:
 107         TagStore *tags;
 108         Buffering *missQueue;
 109         Coherence *coherence;
 110         BaseCache::Params baseParams;
 111         Prefetcher<TagStore, Buffering> *prefetcher;
 112         bool prefetchAccess;
 113         int hitLatency;
 114
 115         Params(TagStore *_tags, Buffering *mq, Coherence *coh,
 116                BaseCache::Params params,
 117                Prefetcher<TagStore, Buffering> *_prefetcher,
 118                bool prefetch_access, int hit_latency)
 119             : tags(_tags), missQueue(mq), coherence(coh),
 120               baseParams(params),
 121               prefetcher(_prefetcher), prefetchAccess(prefetch_access),
 122               hitLatency(hit_latency)
 123         {
 124         }
 125     };
 126
 127     /** Instantiates a basic cache object. */
 128     Cache(const std::string &_name, Params &params);
 129
 130     virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
 131                         bool isCpuSide);
 132
 133     virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
 134
 135     virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
 136
 137     virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 138
 139     void regStats();
 140
 141     /**
 142      * Performs the access specified by the request.
 143      * @param pkt The request to perform.
 144      * @return The result of the access.
 145      */
 146     bool access(Packet * &pkt);
 147
 148     /**
 149      * Selects a request to send on the bus.
 150      * @return The memory request to service.
 151      */
 152     virtual Packet * getPacket();
 153
 154     /**
 155      * Was the request was sent successfully?
 156      * @param pkt The request.
 157      * @param success True if the request was sent successfully.
 158      */
 159     virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
 160
 161     /**
 162      * Was the CSHR request was sent successfully?
 163      * @param pkt The request.
 164      * @param success True if the request was sent successfully.
 165      */
 166     virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
 167
 168     /**
 169      * Handles a response (cache line fill/write ack) from the bus.
 170      * @param pkt The request being responded to.
 171      */
 172     void handleResponse(Packet * &pkt);
 173
 174     /**
 175      * Selects a coherence message to forward to lower levels of the hierarchy.
 176      * @return The coherence message to forward.
 177      */
 178     virtual Packet * getCoherencePacket();
 179
 180     /**
 181      * Snoops bus transactions to maintain coherence.
 182      * @param pkt The current bus transaction.
 183      */
 184     void snoop(Packet * &pkt);
 185
 186     void snoopResponse(Packet * &pkt);
 187
 188     /**
 189      * Invalidates the block containing address if found.
 190      * @param addr The address to look for.
 191      * @param asid The address space ID of the address.
 192      * @todo Is this function necessary?
 193      */
 194     void invalidateBlk(Addr addr);
 195
 196     /**
 197      * Squash all requests associated with specified thread.
 198      * intended for use by I-cache.
 199      * @param threadNum The thread to squash.
 200      */
 201     void squash(int threadNum)
 202     {
 203         missQueue->squash(threadNum);
 204     }
 205
 206     /**
 207      * Return the number of outstanding misses in a Cache.
 208      * Default returns 0.
 209      *
 210      * @retval unsigned The number of missing still outstanding.
 211      */
 212     unsigned outstandingMisses() const
 213     {
 214         return missQueue->getMisses();
 215     }
 216
 217     /**
 218      * Perform the access specified in the request and return the estimated
 219      * time of completion. This function can either update the hierarchy state
 220      * or just perform the access wherever the data is found depending on the
 221      * state of the update flag.
 222      * @param pkt The memory request to satisfy
 223      * @param update If true, update the hierarchy, otherwise just perform the
 224      * request.
 225      * @return The estimated completion time.
 226      */
 227     Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
 228
 229     /**
 230      * Snoop for the provided request in the cache and return the estimated
 231      * time of completion.
 232      * @todo Can a snoop probe not change state?
 233      * @param pkt The memory request to satisfy
 234      * @param update If true, update the hierarchy, otherwise just perform the
 235      * request.
 236      * @return The estimated completion time.
 237      */
 238     Tick snoopProbe(Packet * &pkt);
 239 };
 240
 241 #endif // __CACHE_HH__