src/mem/cache/cache.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Steve Reinhardt
  31  */
  32
  33 /**
  34  * @file
  35  * Describes a cache based on template policies.
  36  */
  37
  38 #ifndef __CACHE_HH__
  39 #define __CACHE_HH__
  40
  41 #include "base/misc.hh" // fatal, panic, and warn
  42 #include "cpu/smt.hh" // SMT_MAX_THREADS
  43
  44 #include "mem/cache/base_cache.hh"
  45 #include "mem/cache/prefetch/prefetcher.hh"
  46
  47 //Forward decleration
  48 class MSHR;
  49
  50
  51 /**
  52  * A template-policy based cache. The behavior of the cache can be altered by
  53  * supplying different template policies. TagStore handles all tag and data
  54  * storage @sa TagStore. Buffering handles all misses and writes/writebacks
  55  * @sa MissQueue. Coherence handles all coherence policy details @sa
  56  * UniCoherence, SimpleMultiCoherence.
  57  */
  58 template <class TagStore, class Buffering, class Coherence>
  59 class Cache : public BaseCache
  60 {
  61   public:
  62     /** Define the type of cache block to use. */
  63     typedef typename TagStore::BlkType BlkType;
  64
  65     bool prefetchAccess;
  66   protected:
  67
  68     /** Tag and data Storage */
  69     TagStore *tags;
  70     /** Miss and Writeback handler */
  71     Buffering *missQueue;
  72     /** Coherence protocol. */
  73     Coherence *coherence;
  74
  75     /** Prefetcher */
  76     Prefetcher<TagStore, Buffering> *prefetcher;
  77
  78     /** Do fast copies in this cache. */
  79     bool doCopy;
  80
  81     /** Block on a delayed copy. */
  82     bool blockOnCopy;
  83
  84     /**
  85      * The clock ratio of the outgoing bus.
  86      * Used for calculating critical word first.
  87      */
  88     int busRatio;
  89
  90      /**
  91       * The bus width in bytes of the outgoing bus.
  92       * Used for calculating critical word first.
  93       */
  94     int busWidth;
  95
  96     /**
  97      * The latency of a hit in this device.
  98      */
  99     int hitLatency;
 100
 101      /**
 102       * A permanent mem req to always be used to cause invalidations.
 103       * Used to append to target list, to cause an invalidation.
 104       */
 105     Packet * invalidatePkt;
 106
 107     /**
 108      * Temporarily move a block into a MSHR.
 109      * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
 110      */
 111     void pseudoFill(Addr addr);
 112
 113     /**
 114      * Temporarily move a block into an existing MSHR.
 115      * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
 116      */
 117     void pseudoFill(MSHR *mshr);
 118
 119   public:
 120
 121     class Params
 122     {
 123       public:
 124         TagStore *tags;
 125         Buffering *missQueue;
 126         Coherence *coherence;
 127         bool doCopy;
 128         bool blockOnCopy;
 129         BaseCache::Params baseParams;
 130         Prefetcher<TagStore, Buffering> *prefetcher;
 131         bool prefetchAccess;
 132         int hitLatency;
 133
 134         Params(TagStore *_tags, Buffering *mq, Coherence *coh,
 135                bool do_copy, BaseCache::Params params,
 136                Prefetcher<TagStore, Buffering> *_prefetcher,
 137                bool prefetch_access, int hit_latency)
 138             : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
 139               blockOnCopy(false), baseParams(params),
 140               prefetcher(_prefetcher), prefetchAccess(prefetch_access),
 141               hitLatency(hit_latency)
 142         {
 143         }
 144     };
 145
 146     /** Instantiates a basic cache object. */
 147     Cache(const std::string &_name, Params &params);
 148
 149     virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
 150                         bool isCpuSide);
 151
 152     virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
 153
 154     virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
 155
 156     virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 157
 158     void regStats();
 159
 160     /**
 161      * Performs the access specified by the request.
 162      * @param pkt The request to perform.
 163      * @return The result of the access.
 164      */
 165     bool access(Packet * &pkt);
 166
 167     /**
 168      * Selects a request to send on the bus.
 169      * @return The memory request to service.
 170      */
 171     virtual Packet * getPacket();
 172
 173     /**
 174      * Was the request was sent successfully?
 175      * @param pkt The request.
 176      * @param success True if the request was sent successfully.
 177      */
 178     virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
 179
 180     /**
 181      * Handles a response (cache line fill/write ack) from the bus.
 182      * @param pkt The request being responded to.
 183      */
 184     void handleResponse(Packet * &pkt);
 185
 186     /**
 187      * Start handling a copy transaction.
 188      * @param pkt The copy request to perform.
 189      */
 190     void startCopy(Packet * &pkt);
 191
 192     /**
 193      * Handle a delayed copy transaction.
 194      * @param pkt The delayed copy request to continue.
 195      * @param addr The address being responded to.
 196      * @param blk The block of the current response.
 197      * @param mshr The mshr being handled.
 198      */
 199     void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
 200
 201     /**
 202      * Selects a coherence message to forward to lower levels of the hierarchy.
 203      * @return The coherence message to forward.
 204      */
 205     virtual Packet * getCoherencePacket();
 206
 207     /**
 208      * Snoops bus transactions to maintain coherence.
 209      * @param pkt The current bus transaction.
 210      */
 211     void snoop(Packet * &pkt);
 212
 213     void snoopResponse(Packet * &pkt);
 214
 215     /**
 216      * Invalidates the block containing address if found.
 217      * @param addr The address to look for.
 218      * @param asid The address space ID of the address.
 219      * @todo Is this function necessary?
 220      */
 221     void invalidateBlk(Addr addr);
 222
 223     /**
 224      * Squash all requests associated with specified thread.
 225      * intended for use by I-cache.
 226      * @param threadNum The thread to squash.
 227      */
 228     void squash(int threadNum)
 229     {
 230         missQueue->squash(threadNum);
 231     }
 232
 233     /**
 234      * Return the number of outstanding misses in a Cache.
 235      * Default returns 0.
 236      *
 237      * @retval unsigned The number of missing still outstanding.
 238      */
 239     unsigned outstandingMisses() const
 240     {
 241         return missQueue->getMisses();
 242     }
 243
 244     /**
 245      * Perform the access specified in the request and return the estimated
 246      * time of completion. This function can either update the hierarchy state
 247      * or just perform the access wherever the data is found depending on the
 248      * state of the update flag.
 249      * @param pkt The memory request to satisfy
 250      * @param update If true, update the hierarchy, otherwise just perform the
 251      * request.
 252      * @return The estimated completion time.
 253      */
 254     Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
 255
 256     /**
 257      * Snoop for the provided request in the cache and return the estimated
 258      * time of completion.
 259      * @todo Can a snoop probe not change state?
 260      * @param pkt The memory request to satisfy
 261      * @param update If true, update the hierarchy, otherwise just perform the
 262      * request.
 263      * @return The estimated completion time.
 264      */
 265     Tick snoopProbe(Packet * &pkt);
 266 };
 267
 268 #endif // __CACHE_HH__