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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/compression/base.hh"
43 #include "base/misc.hh" // fatal, panic, and warn
44 #include "cpu/smt.hh" // SMT_MAX_THREADS
46 #include "mem/cache/base_cache.hh"
47 #include "mem/cache/cache_blk.hh"
48 #include "mem/cache/miss/mshr.hh"
50 #include "sim/eventq.hh"
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
62 template <class TagStore, class Coherence>
63 class Cache : public BaseCache
66 /** Define the type of cache block to use. */
67 typedef typename TagStore::BlkType BlkType;
68 /** A typedef for a list of BlkType pointers. */
69 typedef typename TagStore::BlkList BlkList;
75 class CpuSidePort : public CachePort
78 CpuSidePort(const std::string &_name,
79 Cache<TagStore,Coherence> *_cache);
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
91 virtual bool recvTiming(PacketPtr pkt);
93 virtual Tick recvAtomic(PacketPtr pkt);
95 virtual void recvFunctional(PacketPtr pkt);
98 class MemSidePort : public CachePort
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
113 void processSendEvent();
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
118 virtual bool recvTiming(PacketPtr pkt);
120 virtual void recvRetry();
122 virtual Tick recvAtomic(PacketPtr pkt);
124 virtual void recvFunctional(PacketPtr pkt);
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
130 /** Tag and data Storage */
133 /** Coherence protocol. */
134 Coherence *coherence;
137 BasePrefetcher *prefetcher;
139 /** Temporary cache block for occasional transitory use */
143 * Can this cache should allocate a block on a line-sized write miss.
145 const bool doFastWrites;
147 const bool prefetchMiss;
150 * Handle a replacement for the given request.
151 * @param blk A pointer to the block, usually NULL
152 * @param pkt The memory request to satisfy.
153 * @param new_state The new state of the block.
154 * @param writebacks A list to store any generated writebacks.
156 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
157 CacheBlk::State new_state, PacketList &writebacks);
160 * Does all the processing necessary to perform the provided request.
161 * @param pkt The memory request to perform.
162 * @param lat The latency of the access.
163 * @param writebacks List for any writebacks that need to be performed.
164 * @param update True if the replacement data should be updated.
165 * @return Pointer to the cache block touched by the request. NULL if it
168 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
171 *Handle doing the Compare and Swap function for SPARC.
173 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
176 * Populates a cache block and handles all outstanding requests for the
177 * satisfied fill request. This version takes two memory requests. One
178 * contains the fill data, the other is an optional target to satisfy.
179 * Used for Cache::probe.
180 * @param pkt The memory request with the fill data.
181 * @param blk The cache block if it already exists.
182 * @param writebacks List for any writebacks that need to be performed.
183 * @return Pointer to the new cache block.
185 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
186 PacketList &writebacks);
188 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
189 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
191 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
192 bool already_copied);
195 * Sets the blk to the new state.
196 * @param blk The cache block being snooped.
197 * @param new_state The new coherence state for the block.
199 void handleSnoop(PacketPtr ptk, BlkType *blk,
200 bool is_timing, bool is_deferred);
203 * Create a writeback request for the given block.
204 * @param blk The block to writeback.
205 * @return The writeback request for the block.
207 PacketPtr writebackBlk(BlkType *blk);
215 Coherence *coherence;
216 BaseCache::Params baseParams;
217 BasePrefetcher*prefetcher;
219 const bool doFastWrites;
220 const bool prefetchMiss;
222 Params(TagStore *_tags, Coherence *coh,
223 BaseCache::Params params,
224 BasePrefetcher *_prefetcher,
225 bool prefetch_access, int hit_latency,
228 : tags(_tags), coherence(coh),
230 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
231 doFastWrites(do_fast_writes),
232 prefetchMiss(prefetch_miss)
237 /** Instantiates a basic cache object. */
238 Cache(const std::string &_name, Params ¶ms);
240 virtual Port *getPort(const std::string &if_name, int idx = -1);
241 virtual void deletePortRefs(Port *p);
246 * Performs the access specified by the request.
247 * @param pkt The request to perform.
248 * @return The result of the access.
250 bool timingAccess(PacketPtr pkt);
253 * Performs the access specified by the request.
254 * @param pkt The request to perform.
255 * @return The result of the access.
257 Tick atomicAccess(PacketPtr pkt);
260 * Performs the access specified by the request.
261 * @param pkt The request to perform.
262 * @return The result of the access.
264 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
267 * Handles a response (cache line fill/write ack) from the bus.
268 * @param pkt The request being responded to.
270 void handleResponse(PacketPtr pkt);
273 * Snoops bus transactions to maintain coherence.
274 * @param pkt The current bus transaction.
276 void snoopTiming(PacketPtr pkt);
279 * Snoop for the provided request in the cache and return the estimated
280 * time of completion.
281 * @param pkt The memory request to snoop
282 * @return The estimated completion time.
284 Tick snoopAtomic(PacketPtr pkt);
287 * Squash all requests associated with specified thread.
288 * intended for use by I-cache.
289 * @param threadNum The thread to squash.
291 void squash(int threadNum);
294 * Selects a outstanding request to service.
295 * @return The request to service, NULL if none found.
297 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
298 bool needsExclusive);
300 PacketPtr getTimingPacket();
303 * Marks a request as in service (sent on the bus). This can have side
304 * effect since storage for no response commands is deallocated once they
305 * are successfully sent.
306 * @param pkt The request that was sent on the bus.
308 void markInService(MSHR *mshr);
311 * Perform the given writeback request.
312 * @param pkt The writeback request.
314 void doWriteback(PacketPtr pkt);
317 * Return whether there are any outstanding misses.
319 bool outstandingMisses() const
321 return mshrQueue.allocated != 0;
324 CacheBlk *findBlock(Addr addr) {
325 return tags->findBlock(addr);
328 bool inCache(Addr addr) {
329 return (tags->findBlock(addr) != 0);
332 bool inMissQueue(Addr addr) {
333 return (mshrQueue.findMatch(addr) != 0);
337 #endif // __CACHE_HH__