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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/misc.hh" // fatal, panic, and warn
44 #include "mem/cache/base.hh"
45 #include "mem/cache/blk.hh"
46 #include "mem/cache/mshr.hh"
48 #include "sim/eventq.hh"
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
58 template <class TagStore>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
71 class CpuSidePort : public CachePort
74 CpuSidePort(const std::string &_name,
75 Cache<TagStore> *_cache,
76 const std::string &_label,
77 std::vector<Range<Addr> > filterRanges);
79 // BaseCache::CachePort just has a BaseCache *; this function
80 // lets us get back the type info we lost when we stored the
81 // cache pointer there.
82 Cache<TagStore> *myCache() {
83 return static_cast<Cache<TagStore> *>(cache);
86 virtual void getDeviceAddressRanges(AddrRangeList &resp,
89 virtual bool recvTiming(PacketPtr pkt);
91 virtual Tick recvAtomic(PacketPtr pkt);
93 virtual void recvFunctional(PacketPtr pkt);
96 class MemSidePort : public CachePort
99 MemSidePort(const std::string &_name,
100 Cache<TagStore> *_cache,
101 const std::string &_label,
102 std::vector<Range<Addr> > filterRanges);
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore> *myCache() {
108 return static_cast<Cache<TagStore> *>(cache);
113 void processSendEvent();
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
118 virtual bool recvTiming(PacketPtr pkt);
120 virtual void recvRetry();
122 virtual Tick recvAtomic(PacketPtr pkt);
124 virtual void recvFunctional(PacketPtr pkt);
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
130 /** Tag and data Storage */
134 BasePrefetcher *prefetcher;
136 /** Temporary cache block for occasional transitory use */
140 * Can this cache should allocate a block on a line-sized write miss.
142 const bool doFastWrites;
144 const bool prefetchMiss;
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
165 bool access(PacketPtr pkt, BlkType *&blk,
166 int &lat, PacketList &writebacks);
169 *Handle doing the Compare and Swap function for SPARC.
171 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
174 * Find a block frame for new block at address addr, assuming that
175 * the block is not currently in the cache. Append writebacks if
176 * any to provided packet list. Return free block frame. May
177 * return NULL if there are no replaceable blocks at the moment.
179 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
182 * Populates a cache block and handles all outstanding requests for the
183 * satisfied fill request. This version takes two memory requests. One
184 * contains the fill data, the other is an optional target to satisfy.
185 * Used for Cache::probe.
186 * @param pkt The memory request with the fill data.
187 * @param blk The cache block if it already exists.
188 * @param writebacks List for any writebacks that need to be performed.
189 * @return Pointer to the new cache block.
191 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
192 PacketList &writebacks);
194 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
195 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
197 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
198 bool already_copied, bool pending_inval);
201 * Sets the blk to the new state.
202 * @param blk The cache block being snooped.
203 * @param new_state The new coherence state for the block.
205 void handleSnoop(PacketPtr ptk, BlkType *blk,
206 bool is_timing, bool is_deferred, bool pending_inval);
209 * Create a writeback request for the given block.
210 * @param blk The block to writeback.
211 * @return The writeback request for the block.
213 PacketPtr writebackBlk(BlkType *blk);
216 /** Instantiates a basic cache object. */
217 Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
219 virtual Port *getPort(const std::string &if_name, int idx = -1);
220 virtual void deletePortRefs(Port *p);
225 * Performs the access specified by the request.
226 * @param pkt The request to perform.
227 * @return The result of the access.
229 bool timingAccess(PacketPtr pkt);
232 * Performs the access specified by the request.
233 * @param pkt The request to perform.
234 * @return The result of the access.
236 Tick atomicAccess(PacketPtr pkt);
239 * Performs the access specified by the request.
240 * @param pkt The request to perform.
241 * @return The result of the access.
243 void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
244 CachePort *otherSidePort);
247 * Handles a response (cache line fill/write ack) from the bus.
248 * @param pkt The request being responded to.
250 void handleResponse(PacketPtr pkt);
253 * Snoops bus transactions to maintain coherence.
254 * @param pkt The current bus transaction.
256 void snoopTiming(PacketPtr pkt);
259 * Snoop for the provided request in the cache and return the estimated
260 * time of completion.
261 * @param pkt The memory request to snoop
262 * @return The estimated completion time.
264 Tick snoopAtomic(PacketPtr pkt);
267 * Squash all requests associated with specified thread.
268 * intended for use by I-cache.
269 * @param threadNum The thread to squash.
271 void squash(int threadNum);
274 * Generate an appropriate downstream bus request packet for the
276 * @param cpu_pkt The upstream request that needs to be satisfied.
277 * @param blk The block currently in the cache corresponding to
278 * cpu_pkt (NULL if none).
279 * @param needsExclusive Indicates that an exclusive copy is required
280 * even if the request in cpu_pkt doesn't indicate that.
281 * @return A new Packet containing the request, or NULL if the
282 * current request in cpu_pkt should just be forwarded on.
284 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
285 bool needsExclusive);
288 * Return the next MSHR to service, either a pending miss from the
289 * mshrQueue, a buffered write from the write buffer, or something
290 * from the prefetcher. This function is responsible for
291 * prioritizing among those sources on the fly.
296 * Selects an outstanding request to service. Called when the
297 * cache gets granted the downstream bus in timing mode.
298 * @return The request to service, NULL if none found.
300 PacketPtr getTimingPacket();
303 * Marks a request as in service (sent on the bus). This can have side
304 * effect since storage for no response commands is deallocated once they
305 * are successfully sent.
306 * @param pkt The request that was sent on the bus.
308 void markInService(MSHR *mshr);
311 * Perform the given writeback request.
312 * @param pkt The writeback request.
314 void doWriteback(PacketPtr pkt);
317 * Return whether there are any outstanding misses.
319 bool outstandingMisses() const
321 return mshrQueue.allocated != 0;
324 CacheBlk *findBlock(Addr addr) {
325 return tags->findBlock(addr);
328 bool inCache(Addr addr) {
329 return (tags->findBlock(addr) != 0);
332 bool inMissQueue(Addr addr) {
333 return (mshrQueue.findMatch(addr) != 0);
337 #endif // __CACHE_HH__