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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/misc.hh" // fatal, panic, and warn
44 #include "mem/cache/base_cache.hh"
45 #include "mem/cache/cache_blk.hh"
46 #include "mem/cache/miss/mshr.hh"
48 #include "sim/eventq.hh"
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
58 template <class TagStore>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
71 class CpuSidePort : public CachePort
74 CpuSidePort(const std::string &_name,
75 Cache<TagStore> *_cache);
77 // BaseCache::CachePort just has a BaseCache *; this function
78 // lets us get back the type info we lost when we stored the
79 // cache pointer there.
80 Cache<TagStore> *myCache() {
81 return static_cast<Cache<TagStore> *>(cache);
84 virtual void getDeviceAddressRanges(AddrRangeList &resp,
87 virtual bool recvTiming(PacketPtr pkt);
89 virtual Tick recvAtomic(PacketPtr pkt);
91 virtual void recvFunctional(PacketPtr pkt);
94 class MemSidePort : public CachePort
97 MemSidePort(const std::string &_name,
98 Cache<TagStore> *_cache);
100 // BaseCache::CachePort just has a BaseCache *; this function
101 // lets us get back the type info we lost when we stored the
102 // cache pointer there.
103 Cache<TagStore> *myCache() {
104 return static_cast<Cache<TagStore> *>(cache);
109 void processSendEvent();
111 virtual void getDeviceAddressRanges(AddrRangeList &resp,
114 virtual bool recvTiming(PacketPtr pkt);
116 virtual void recvRetry();
118 virtual Tick recvAtomic(PacketPtr pkt);
120 virtual void recvFunctional(PacketPtr pkt);
122 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
126 /** Tag and data Storage */
130 BasePrefetcher *prefetcher;
132 /** Temporary cache block for occasional transitory use */
136 * Can this cache should allocate a block on a line-sized write miss.
138 const bool doFastWrites;
140 const bool prefetchMiss;
143 * Handle a replacement for the given request.
144 * @param blk A pointer to the block, usually NULL
145 * @param pkt The memory request to satisfy.
146 * @param new_state The new state of the block.
147 * @param writebacks A list to store any generated writebacks.
149 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
150 CacheBlk::State new_state, PacketList &writebacks);
153 * Does all the processing necessary to perform the provided request.
154 * @param pkt The memory request to perform.
155 * @param lat The latency of the access.
156 * @param writebacks List for any writebacks that need to be performed.
157 * @param update True if the replacement data should be updated.
158 * @return Pointer to the cache block touched by the request. NULL if it
161 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
164 *Handle doing the Compare and Swap function for SPARC.
166 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
169 * Populates a cache block and handles all outstanding requests for the
170 * satisfied fill request. This version takes two memory requests. One
171 * contains the fill data, the other is an optional target to satisfy.
172 * Used for Cache::probe.
173 * @param pkt The memory request with the fill data.
174 * @param blk The cache block if it already exists.
175 * @param writebacks List for any writebacks that need to be performed.
176 * @return Pointer to the new cache block.
178 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
179 PacketList &writebacks);
181 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
182 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
184 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
185 bool already_copied);
188 * Sets the blk to the new state.
189 * @param blk The cache block being snooped.
190 * @param new_state The new coherence state for the block.
192 void handleSnoop(PacketPtr ptk, BlkType *blk,
193 bool is_timing, bool is_deferred,
194 bool lower_mshr_pending);
197 * Create a writeback request for the given block.
198 * @param blk The block to writeback.
199 * @return The writeback request for the block.
201 PacketPtr writebackBlk(BlkType *blk);
209 BaseCache::Params baseParams;
210 BasePrefetcher*prefetcher;
212 const bool doFastWrites;
213 const bool prefetchMiss;
215 Params(TagStore *_tags,
216 BaseCache::Params params,
217 BasePrefetcher *_prefetcher,
218 bool prefetch_access, int hit_latency,
223 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
224 doFastWrites(do_fast_writes),
225 prefetchMiss(prefetch_miss)
230 /** Instantiates a basic cache object. */
231 Cache(const std::string &_name, Params ¶ms);
233 virtual Port *getPort(const std::string &if_name, int idx = -1);
234 virtual void deletePortRefs(Port *p);
239 * Performs the access specified by the request.
240 * @param pkt The request to perform.
241 * @return The result of the access.
243 bool timingAccess(PacketPtr pkt);
246 * Performs the access specified by the request.
247 * @param pkt The request to perform.
248 * @return The result of the access.
250 Tick atomicAccess(PacketPtr pkt);
253 * Performs the access specified by the request.
254 * @param pkt The request to perform.
255 * @return The result of the access.
257 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
260 * Handles a response (cache line fill/write ack) from the bus.
261 * @param pkt The request being responded to.
263 void handleResponse(PacketPtr pkt);
266 * Snoops bus transactions to maintain coherence.
267 * @param pkt The current bus transaction.
269 void snoopTiming(PacketPtr pkt);
272 * Snoop for the provided request in the cache and return the estimated
273 * time of completion.
274 * @param pkt The memory request to snoop
275 * @return The estimated completion time.
277 Tick snoopAtomic(PacketPtr pkt);
280 * Squash all requests associated with specified thread.
281 * intended for use by I-cache.
282 * @param threadNum The thread to squash.
284 void squash(int threadNum);
287 * Selects a outstanding request to service.
288 * @return The request to service, NULL if none found.
290 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
291 bool needsExclusive);
293 PacketPtr getTimingPacket();
296 * Marks a request as in service (sent on the bus). This can have side
297 * effect since storage for no response commands is deallocated once they
298 * are successfully sent.
299 * @param pkt The request that was sent on the bus.
301 void markInService(MSHR *mshr);
304 * Perform the given writeback request.
305 * @param pkt The writeback request.
307 void doWriteback(PacketPtr pkt);
310 * Return whether there are any outstanding misses.
312 bool outstandingMisses() const
314 return mshrQueue.allocated != 0;
317 CacheBlk *findBlock(Addr addr) {
318 return tags->findBlock(addr);
321 bool inCache(Addr addr) {
322 return (tags->findBlock(addr) != 0);
325 bool inMissQueue(Addr addr) {
326 return (mshrQueue.findMatch(addr) != 0);
330 #endif // __CACHE_HH__