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28 * Authors: Erik Hallnor
36 * Describes a cache based on template policies.
42 #include "base/compression/base.hh"
43 #include "base/misc.hh" // fatal, panic, and warn
44 #include "cpu/smt.hh" // SMT_MAX_THREADS
46 #include "mem/cache/base_cache.hh"
47 #include "mem/cache/cache_blk.hh"
48 #include "mem/cache/miss/mshr.hh"
50 #include "sim/eventq.hh"
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
62 template <class TagStore, class Coherence>
63 class Cache : public BaseCache
66 /** Define the type of cache block to use. */
67 typedef typename TagStore::BlkType BlkType;
68 /** A typedef for a list of BlkType pointers. */
69 typedef typename TagStore::BlkList BlkList;
75 class CpuSidePort : public CachePort
78 CpuSidePort(const std::string &_name,
79 Cache<TagStore,Coherence> *_cache);
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
91 virtual bool recvTiming(PacketPtr pkt);
93 virtual Tick recvAtomic(PacketPtr pkt);
95 virtual void recvFunctional(PacketPtr pkt);
98 class MemSidePort : public CachePort
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
113 void processSendEvent();
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
118 virtual bool recvTiming(PacketPtr pkt);
120 virtual void recvRetry();
122 virtual Tick recvAtomic(PacketPtr pkt);
124 virtual void recvFunctional(PacketPtr pkt);
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
130 /** Tag and data Storage */
133 /** Coherence protocol. */
134 Coherence *coherence;
137 BasePrefetcher *prefetcher;
140 * The clock ratio of the outgoing bus.
141 * Used for calculating critical word first.
146 * The bus width in bytes of the outgoing bus.
147 * Used for calculating critical word first.
152 * The latency of a hit in this device.
157 * Can this cache should allocate a block on a line-sized write miss.
159 const bool doFastWrites;
161 const bool prefetchMiss;
164 * Handle a replacement for the given request.
165 * @param blk A pointer to the block, usually NULL
166 * @param pkt The memory request to satisfy.
167 * @param new_state The new state of the block.
168 * @param writebacks A list to store any generated writebacks.
170 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
171 CacheBlk::State new_state, PacketList &writebacks);
174 * Does all the processing necessary to perform the provided request.
175 * @param pkt The memory request to perform.
176 * @param lat The latency of the access.
177 * @param writebacks List for any writebacks that need to be performed.
178 * @param update True if the replacement data should be updated.
179 * @return Pointer to the cache block touched by the request. NULL if it
182 bool access(PacketPtr pkt, BlkType *blk, int & lat);
185 *Handle doing the Compare and Swap function for SPARC.
187 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
190 * Populates a cache block and handles all outstanding requests for the
191 * satisfied fill request. This version takes two memory requests. One
192 * contains the fill data, the other is an optional target to satisfy.
193 * Used for Cache::probe.
194 * @param pkt The memory request with the fill data.
195 * @param blk The cache block if it already exists.
196 * @param writebacks List for any writebacks that need to be performed.
197 * @return Pointer to the new cache block.
199 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
200 PacketList &writebacks);
202 bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
203 bool satisfyTarget(MSHR::Target *target, BlkType *blk);
204 void satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
206 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data);
209 * Sets the blk to the new state.
210 * @param blk The cache block being snooped.
211 * @param new_state The new coherence state for the block.
213 void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing);
216 * Create a writeback request for the given block.
217 * @param blk The block to writeback.
218 * @return The writeback request for the block.
220 PacketPtr writebackBlk(BlkType *blk);
228 Coherence *coherence;
229 BaseCache::Params baseParams;
230 BasePrefetcher*prefetcher;
232 const bool doFastWrites;
233 const bool prefetchMiss;
235 Params(TagStore *_tags, Coherence *coh,
236 BaseCache::Params params,
237 BasePrefetcher *_prefetcher,
238 bool prefetch_access, int hit_latency,
241 : tags(_tags), coherence(coh),
243 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
244 doFastWrites(do_fast_writes),
245 prefetchMiss(prefetch_miss)
250 /** Instantiates a basic cache object. */
251 Cache(const std::string &_name, Params ¶ms);
253 virtual Port *getPort(const std::string &if_name, int idx = -1);
254 virtual void deletePortRefs(Port *p);
259 * Performs the access specified by the request.
260 * @param pkt The request to perform.
261 * @return The result of the access.
263 bool timingAccess(PacketPtr pkt);
266 * Performs the access specified by the request.
267 * @param pkt The request to perform.
268 * @return The result of the access.
270 Tick atomicAccess(PacketPtr pkt);
273 * Performs the access specified by the request.
274 * @param pkt The request to perform.
275 * @return The result of the access.
277 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
280 * Handles a response (cache line fill/write ack) from the bus.
281 * @param pkt The request being responded to.
283 void handleResponse(PacketPtr pkt);
286 * Snoops bus transactions to maintain coherence.
287 * @param pkt The current bus transaction.
289 void snoopTiming(PacketPtr pkt);
292 * Snoop for the provided request in the cache and return the estimated
293 * time of completion.
294 * @param pkt The memory request to snoop
295 * @return The estimated completion time.
297 Tick snoopAtomic(PacketPtr pkt);
300 * Squash all requests associated with specified thread.
301 * intended for use by I-cache.
302 * @param threadNum The thread to squash.
304 void squash(int threadNum);
307 * Allocate a new MSHR or write buffer to handle a miss.
308 * @param pkt The access that missed.
309 * @param time The time to continue processing the miss.
310 * @param isFill Whether to fetch & allocate a block
311 * or just forward the request.
313 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool isFill,
317 * Selects a outstanding request to service.
318 * @return The request to service, NULL if none found.
321 PacketPtr getPacket();
324 * Marks a request as in service (sent on the bus). This can have side
325 * effect since storage for no response commands is deallocated once they
326 * are successfully sent.
327 * @param pkt The request that was sent on the bus.
329 void markInService(MSHR *mshr);
332 * Collect statistics and free resources of a satisfied request.
333 * @param pkt The request that has been satisfied.
334 * @param time The time when the request is satisfied.
336 void handleResponse(PacketPtr pkt, Tick time);
339 * Perform the given writeback request.
340 * @param pkt The writeback request.
342 void doWriteback(PacketPtr pkt);
345 * Return whether there are any outstanding misses.
347 bool outstandingMisses() const
349 return mshrQueue.allocated != 0;
352 CacheBlk *findBlock(Addr addr) {
353 return tags->findBlock(addr);
356 bool inCache(Addr addr) {
357 return (tags->findBlock(addr) != 0);
360 bool inMissQueue(Addr addr) {
361 return (mshrQueue.findMatch(addr) != 0);
365 #endif // __CACHE_HH__