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28 * Authors: Erik Hallnor
35 * Describes a cache based on template policies.
41 #include "base/misc.hh" // fatal, panic, and warn
42 #include "cpu/smt.hh" // SMT_MAX_THREADS
44 #include "mem/cache/base_cache.hh"
45 #include "mem/cache/prefetch/prefetcher.hh"
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
58 template <class TagStore, class Buffering, class Coherence>
59 class Cache : public BaseCache
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
68 /** Tag and data Storage */
70 /** Miss and Writeback handler */
72 /** Coherence protocol. */
76 Prefetcher<TagStore, Buffering> *prefetcher;
78 /** Do fast copies in this cache. */
81 /** Block on a delayed copy. */
85 * The clock ratio of the outgoing bus.
86 * Used for calculating critical word first.
91 * The bus width in bytes of the outgoing bus.
92 * Used for calculating critical word first.
97 * The latency of a hit in this device.
102 * A permanent mem req to always be used to cause invalidations.
103 * Used to append to target list, to cause an invalidation.
105 Packet * invalidatePkt;
108 * Temporarily move a block into a MSHR.
109 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
111 void pseudoFill(Addr addr, int asid);
114 * Temporarily move a block into an existing MSHR.
115 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
117 void pseudoFill(MSHR *mshr);
125 Buffering *missQueue;
126 Coherence *coherence;
129 BaseCache::Params baseParams;
130 Prefetcher<TagStore, Buffering> *prefetcher;
134 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
135 bool do_copy, BaseCache::Params params,
136 Prefetcher<TagStore, Buffering> *_prefetcher,
137 bool prefetch_access, int hit_latency)
138 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
139 blockOnCopy(false), baseParams(params),
140 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
141 hitLatency(hit_latency)
146 /** Instantiates a basic cache object. */
147 Cache(const std::string &_name, Params ¶ms);
149 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
152 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
154 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
156 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
161 * Performs the access specified by the request.
162 * @param req The request to perform.
163 * @return The result of the access.
165 bool access(Packet * &pkt);
168 * Selects a request to send on the bus.
169 * @return The memory request to service.
171 Packet * getPacket();
174 * Was the request was sent successfully?
175 * @param req The request.
176 * @param success True if the request was sent successfully.
178 void sendResult(Packet * &pkt, bool success);
181 * Handles a response (cache line fill/write ack) from the bus.
182 * @param req The request being responded to.
184 void handleResponse(Packet * &pkt);
187 * Start handling a copy transaction.
188 * @param req The copy request to perform.
190 void startCopy(Packet * &pkt);
193 * Handle a delayed copy transaction.
194 * @param req The delayed copy request to continue.
195 * @param addr The address being responded to.
196 * @param blk The block of the current response.
197 * @param mshr The mshr being handled.
199 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
202 * Selects a coherence message to forward to lower levels of the hierarchy.
203 * @return The coherence message to forward.
205 Packet * getCoherenceReq();
208 * Snoops bus transactions to maintain coherence.
209 * @param req The current bus transaction.
211 void snoop(Packet * &pkt);
213 void snoopResponse(Packet * &pkt);
216 * Invalidates the block containing address if found.
217 * @param addr The address to look for.
218 * @param asid The address space ID of the address.
219 * @todo Is this function necessary?
221 void invalidateBlk(Addr addr, int asid);
224 * Aquash all requests associated with specified thread.
225 * intended for use by I-cache.
226 * @param req->getThreadNum()ber The thread to squash.
228 void squash(int threadNum)
230 missQueue->squash(threadNum);
234 * Return the number of outstanding misses in a Cache.
237 * @retval unsigned The number of missing still outstanding.
239 unsigned outstandingMisses() const
241 return missQueue->getMisses();
245 * Send a response to the slave interface.
246 * @param req The request being responded to.
247 * @param time The time the response is ready.
249 void respond(Packet * &pkt, Tick time)
251 //si->respond(pkt,time);
252 cpuSidePort->sendAtomic(pkt);
256 * Perform the access specified in the request and return the estimated
257 * time of completion. This function can either update the hierarchy state
258 * or just perform the access wherever the data is found depending on the
259 * state of the update flag.
260 * @param req The memory request to satisfy
261 * @param update If true, update the hierarchy, otherwise just perform the
263 * @return The estimated completion time.
265 Tick probe(Packet * &pkt, bool update);
268 * Snoop for the provided request in the cache and return the estimated
269 * time of completion.
270 * @todo Can a snoop probe not change state?
271 * @param req The memory request to satisfy
272 * @param update If true, update the hierarchy, otherwise just perform the
274 * @return The estimated completion time.
276 Tick snoopProbe(Packet * &pkt, bool update);
279 #endif // __CACHE_HH__