src/mem/cache/cache_blk.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /** @file
  32  * Definitions of a simple cache block class.
  33  */
  34
  35 #ifndef __CACHE_BLK_HH__
  36 #define __CACHE_BLK_HH__
  37
  38 #include "sim/root.hh"          // for Tick
  39 #include "arch/isa_traits.hh"   // for Addr
  40
  41 #include <iostream>
  42
  43 /**
  44  * Cache block status bit assignments
  45  */
  46 enum CacheBlkStatusBits {
  47     /** valid, readable */
  48     BlkValid =          0x01,
  49     /** write permission */
  50     BlkWritable =       0x02,
  51     /** dirty (modified) */
  52     BlkDirty =          0x04,
  53     /** compressed */
  54     BlkCompressed =     0x08,
  55     /** block was referenced */
  56     BlkReferenced =     0x10,
  57     /** block was a hardware prefetch yet unaccessed*/
  58     BlkHWPrefetched =   0x20
  59 };
  60
  61 /**
  62  * A Basic Cache block.
  63  * Contains the tag, status, and a pointer to data.
  64  */
  65 class CacheBlk
  66 {
  67   public:
  68     /** The address space ID of this block. */
  69     int asid;
  70     /** Data block tag value. */
  71     Addr tag;
  72     /**
  73      * Contains a copy of the data in this block for easy access. This is used
  74      * for efficient execution when the data could be actually stored in
  75      * another format (COW, compressed, sub-blocked, etc). In all cases the
  76      * data stored here should be kept consistant with the actual data
  77      * referenced by this block.
  78      */
  79     uint8_t *data;
  80     /** the number of bytes stored in this block. */
  81     int size;
  82
  83     /** block state: OR of CacheBlkStatusBit */
  84     typedef unsigned State;
  85
  86     /** The current status of this block. @sa CacheBlockStatusBits */
  87     State status;
  88
  89     /** Which curTick will this block be accessable */
  90     Tick whenReady;
  91
  92     /**
  93      * The set this block belongs to.
  94      * @todo Move this into subclasses when we fix CacheTags to use them.
  95      */
  96     int set;
  97
  98     /** Number of references to this block since it was brought in. */
  99     int refCount;
 100
 101     CacheBlk()
 102         : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 103           set(-1), refCount(0)
 104     {}
 105
 106     /**
 107      * Copy the state of the given block into this one.
 108      * @param rhs The block to copy.
 109      * @return a const reference to this block.
 110      */
 111     const CacheBlk& operator=(const CacheBlk& rhs)
 112     {
 113         asid = rhs.asid;
 114         tag = rhs.tag;
 115         data = rhs.data;
 116         size = rhs.size;
 117         status = rhs.status;
 118         whenReady = rhs.whenReady;
 119         set = rhs.set;
 120         refCount = rhs.refCount;
 121         return *this;
 122     }
 123
 124     /**
 125      * Checks the write permissions of this block.
 126      * @return True if the block is writable.
 127      */
 128     bool isWritable() const
 129     {
 130         const int needed_bits = BlkWritable | BlkValid;
 131         return (status & needed_bits) == needed_bits;
 132     }
 133
 134     /**
 135      * Checks that a block is valid (readable).
 136      * @return True if the block is valid.
 137      */
 138     bool isValid() const
 139     {
 140         return (status & BlkValid) != 0;
 141     }
 142
 143     /**
 144      * Check to see if a block has been written.
 145      * @return True if the block is dirty.
 146      */
 147     bool isModified() const
 148     {
 149         return (status & BlkDirty) != 0;
 150     }
 151
 152     /**
 153      * Check to see if this block contains compressed data.
 154      * @return True iF the block's data is compressed.
 155      */
 156     bool isCompressed() const
 157     {
 158         return (status & BlkCompressed) != 0;
 159     }
 160
 161     /**
 162      * Check if this block has been referenced.
 163      * @return True if the block has been referenced.
 164      */
 165     bool isReferenced() const
 166     {
 167         return (status & BlkReferenced) != 0;
 168     }
 169
 170     /**
 171      * Check if this block was the result of a hardware prefetch, yet to
 172      * be touched.
 173      * @return True if the block was a hardware prefetch, unaccesed.
 174      */
 175     bool isPrefetch() const
 176     {
 177         return (status & BlkHWPrefetched) != 0;
 178     }
 179
 180
 181 };
 182
 183 /**
 184  * Output a CacheBlk to the given ostream.
 185  * @param out The stream for the output.
 186  * @param blk The cache block to print.
 187  *
 188  * @return The output stream.
 189  */
 190 inline std::ostream &
 191 operator<<(std::ostream &out, const CacheBlk &blk)
 192 {
 193     out << std::hex << std::endl;
 194     out << "  Tag: " << blk.tag << std::endl;
 195     out << "  Status: " <<  blk.status << std::endl;
 196
 197     return(out << std::dec);
 198 }
 199
 200 #endif //__CACHE_BLK_HH__