src/mem/cache/cache_blk.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /** @file
  32  * Definitions of a simple cache block class.
  33  */
  34
  35 #ifndef __CACHE_BLK_HH__
  36 #define __CACHE_BLK_HH__
  37
  38 #include "sim/root.hh"          // for Tick
  39 #include "arch/isa_traits.hh"   // for Addr
  40
  41 /**
  42  * Cache block status bit assignments
  43  */
  44 enum CacheBlkStatusBits {
  45     /** valid, readable */
  46     BlkValid =          0x01,
  47     /** write permission */
  48     BlkWritable =       0x02,
  49     /** dirty (modified) */
  50     BlkDirty =          0x04,
  51     /** compressed */
  52     BlkCompressed =     0x08,
  53     /** block was referenced */
  54     BlkReferenced =     0x10,
  55     /** block was a hardware prefetch yet unaccessed*/
  56     BlkHWPrefetched =   0x20
  57 };
  58
  59 /**
  60  * A Basic Cache block.
  61  * Contains the tag, status, and a pointer to data.
  62  */
  63 class CacheBlk
  64 {
  65   public:
  66     /** The address space ID of this block. */
  67     int asid;
  68     /** Data block tag value. */
  69     Addr tag;
  70     /**
  71      * Contains a copy of the data in this block for easy access. This is used
  72      * for efficient execution when the data could be actually stored in
  73      * another format (COW, compressed, sub-blocked, etc). In all cases the
  74      * data stored here should be kept consistant with the actual data
  75      * referenced by this block.
  76      */
  77     uint8_t *data;
  78     /** the number of bytes stored in this block. */
  79     int size;
  80
  81     /** block state: OR of CacheBlkStatusBit */
  82     typedef unsigned State;
  83
  84     /** The current status of this block. @sa CacheBlockStatusBits */
  85     State status;
  86
  87     /** Which curTick will this block be accessable */
  88     Tick whenReady;
  89
  90     /**
  91      * The set this block belongs to.
  92      * @todo Move this into subclasses when we fix CacheTags to use them.
  93      */
  94     int set;
  95
  96     /** Number of references to this block since it was brought in. */
  97     int refCount;
  98
  99     CacheBlk()
 100         : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
 101           set(-1), refCount(0)
 102     {}
 103
 104     /**
 105      * Copy the state of the given block into this one.
 106      * @param rhs The block to copy.
 107      * @return a const reference to this block.
 108      */
 109     const CacheBlk& operator=(const CacheBlk& rhs)
 110     {
 111         asid = rhs.asid;
 112         tag = rhs.tag;
 113         data = rhs.data;
 114         size = rhs.size;
 115         status = rhs.status;
 116         whenReady = rhs.whenReady;
 117         set = rhs.set;
 118         refCount = rhs.refCount;
 119         return *this;
 120     }
 121
 122     /**
 123      * Checks the write permissions of this block.
 124      * @return True if the block is writable.
 125      */
 126     bool isWritable() const
 127     {
 128         const int needed_bits = BlkWritable | BlkValid;
 129         return (status & needed_bits) == needed_bits;
 130     }
 131
 132     /**
 133      * Checks that a block is valid (readable).
 134      * @return True if the block is valid.
 135      */
 136     bool isValid() const
 137     {
 138         return (status & BlkValid) != 0;
 139     }
 140
 141     /**
 142      * Check to see if a block has been written.
 143      * @return True if the block is dirty.
 144      */
 145     bool isModified() const
 146     {
 147         return (status & BlkDirty) != 0;
 148     }
 149
 150     /**
 151      * Check to see if this block contains compressed data.
 152      * @return True iF the block's data is compressed.
 153      */
 154     bool isCompressed() const
 155     {
 156         return (status & BlkCompressed) != 0;
 157     }
 158
 159     /**
 160      * Check if this block has been referenced.
 161      * @return True if the block has been referenced.
 162      */
 163     bool isReferenced() const
 164     {
 165         return (status & BlkReferenced) != 0;
 166     }
 167
 168     /**
 169      * Check if this block was the result of a hardware prefetch, yet to
 170      * be touched.
 171      * @return True if the block was a hardware prefetch, unaccesed.
 172      */
 173     bool isPrefetch() const
 174     {
 175         return (status & BlkHWPrefetched) != 0;
 176     }
 177
 178
 179 };
 180
 181 /**
 182  * Output a CacheBlk to the given ostream.
 183  * @param out The stream for the output.
 184  * @param blk The cache block to print.
 185  *
 186  * @return The output stream.
 187  */
 188 inline std::ostream &
 189 operator<<(std::ostream &out, const CacheBlk &blk)
 190 {
 191     out << std::hex << std::endl;
 192     out << "  Tag: " << blk.tag << std::endl;
 193     out << "  Status: " <<  blk.status << std::endl;
 194
 195     return(out << std::dec);
 196 }
 197
 198 #endif //__CACHE_BLK_HH__