src/mem/cache/cache_builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "mem/config/cache.hh"
  40 #include "mem/config/compression.hh"
  41 #include "mem/config/prefetch.hh"
  42
  43 #include "mem/cache/base_cache.hh"
  44 #include "mem/cache/cache.hh"
  45 #include "mem/bus.hh"
  46 #include "mem/cache/coherence/coherence_protocol.hh"
  47 #include "sim/builder.hh"
  48
  49 // Tag Templates
  50 #if defined(USE_CACHE_LRU)
  51 #include "mem/cache/tags/lru.hh"
  52 #endif
  53
  54 #if defined(USE_CACHE_FALRU)
  55 #include "mem/cache/tags/fa_lru.hh"
  56 #endif
  57
  58 #if defined(USE_CACHE_IIC)
  59 #include "mem/cache/tags/iic.hh"
  60 #endif
  61
  62 #if defined(USE_CACHE_SPLIT)
  63 #include "mem/cache/tags/split.hh"
  64 #endif
  65
  66 #if defined(USE_CACHE_SPLIT_LIFO)
  67 #include "mem/cache/tags/split_lifo.hh"
  68 #endif
  69
  70 // Compression Templates
  71 #include "base/compression/null_compression.hh"
  72 #if defined(USE_LZSS_COMPRESSION)
  73 #include "base/compression/lzss_compression.hh"
  74 #endif
  75
  76 // CacheTags Templates
  77 #include "mem/cache/tags/cache_tags.hh"
  78
  79 // MissQueue Templates
  80 #include "mem/cache/miss/miss_queue.hh"
  81 #include "mem/cache/miss/blocking_buffer.hh"
  82
  83 // Coherence Templates
  84 #include "mem/cache/coherence/uni_coherence.hh"
  85 #include "mem/cache/coherence/simple_coherence.hh"
  86
  87 //Prefetcher Headers
  88 #if defined(USE_GHB)
  89 #include "mem/cache/prefetch/ghb_prefetcher.hh"
  90 #endif
  91 #if defined(USE_TAGGED)
  92 #include "mem/cache/prefetch/tagged_prefetcher.hh"
  93 #endif
  94 #if defined(USE_STRIDED)
  95 #include "mem/cache/prefetch/stride_prefetcher.hh"
  96 #endif
  97
  98
  99 using namespace std;
 100 using namespace TheISA;
 101
 102 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 103
 104 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 105
 106     Param<int> size;
 107     Param<int> assoc;
 108     Param<int> block_size;
 109     Param<int> latency;
 110     Param<int> mshrs;
 111     Param<int> tgts_per_mshr;
 112     Param<int> write_buffers;
 113     Param<bool> prioritizeRequests;
 114 //    SimObjectParam<Bus *> in_bus;
 115 //    SimObjectParam<Bus *> out_bus;
 116     SimObjectParam<CoherenceProtocol *> protocol;
 117     Param<Addr> trace_addr;
 118     Param<int> hash_delay;
 119 #if defined(USE_CACHE_IIC)
 120     SimObjectParam<Repl *> repl;
 121 #endif
 122     Param<bool> compressed_bus;
 123     Param<bool> store_compressed;
 124     Param<bool> adaptive_compression;
 125     Param<int> compression_latency;
 126     Param<int> subblock_size;
 127     Param<Counter> max_miss_count;
 128 //    SimObjectParam<HierParams *> hier;
 129     VectorParam<Range<Addr> > addr_range;
 130 //    SimObjectParam<MemTraceWriter *> mem_trace;
 131     Param<bool> split;
 132     Param<int> split_size;
 133     Param<bool> lifo;
 134     Param<bool> two_queue;
 135     Param<bool> prefetch_miss;
 136     Param<bool> prefetch_access;
 137     Param<int> prefetcher_size;
 138     Param<bool> prefetch_past_page;
 139     Param<bool> prefetch_serial_squash;
 140     Param<Tick> prefetch_latency;
 141     Param<int> prefetch_degree;
 142     Param<string> prefetch_policy;
 143     Param<bool> prefetch_cache_check_push;
 144     Param<bool> prefetch_use_cpu_id;
 145     Param<bool> prefetch_data_accesses_only;
 146     Param<int> hit_latency;
 147
 148 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 149
 150
 151 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
 152
 153     INIT_PARAM(size, "capacity in bytes"),
 154     INIT_PARAM(assoc, "associativity"),
 155     INIT_PARAM(block_size, "block size in bytes"),
 156     INIT_PARAM(latency, "hit latency in CPU cycles"),
 157     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
 158     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
 159     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
 160     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
 161                     false),
 162 /*    INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL),
 163     INIT_PARAM(out_bus, "outgoing bus object"),
 164 */
 165     INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
 166     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 167
 168     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
 169 #if defined(USE_CACHE_IIC)
 170     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
 171 #endif
 172     INIT_PARAM_DFLT(compressed_bus,
 173                     "This cache connects to a compressed memory",
 174                     false),
 175     INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
 176                     false),
 177     INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
 178                     false),
 179     INIT_PARAM_DFLT(compression_latency,
 180                     "Latency in cycles of compression algorithm",
 181                     0),
 182     INIT_PARAM_DFLT(subblock_size,
 183                     "Size of subblock in IIC used for compression",
 184                     0),
 185     INIT_PARAM_DFLT(max_miss_count,
 186                     "The number of misses to handle before calling exit",
 187                     0),
 188 /*    INIT_PARAM_DFLT(hier,
 189                     "Hierarchy global variables",
 190                     &defaultHierParams),
 191 */
 192     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
 193                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
 194 //    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
 195     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
 196     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
 197     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
 198     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
 199     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
 200     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
 201     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
 202     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
 203     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
 204     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
 205     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
 206     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
 207     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
 208     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
 209     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false),
 210     INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1)
 211 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 212
 213
 214 #define BUILD_CACHE(t, comp, b, c) do {                                 \
 215         Prefetcher<CacheTags<t, comp>, b> *pf; \
 216         if (pf_policy == "tagged") {      \
 217              BUILD_TAGGED_PREFETCHER(t, comp, b); \
 218         }            \
 219         else if (pf_policy == "stride") {       \
 220              BUILD_STRIDED_PREFETCHER(t, comp, b); \
 221         } \
 222         else if (pf_policy == "ghb") {       \
 223              BUILD_GHB_PREFETCHER(t, comp, b); \
 224         } \
 225         else { \
 226              BUILD_NULL_PREFETCHER(t, comp, b); \
 227         } \
 228         Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
 229                                                        base_params, \
 230                                                        /*in_bus, out_bus,*/ pf,  \
 231                                                        prefetch_access, hit_latency); \
 232         Cache<CacheTags<t, comp>, b, c> *retval =                       \
 233             new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
 234                                                 params);                \
 235 /*      if (in_bus == NULL) {                                           \
 236             retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
 237         } else {                                                        \
 238             retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
 239         }                                                               \
 240         retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
 241         out_bus->rangeChange();                                         \
 242         return retval;                                                  \
 243 */return retval;                                                          \
 244     } while (0)
 245
 246 #define BUILD_CACHE_PANIC(x) do {                       \
 247         panic("%s not compiled into M5", x);            \
 248     } while (0)
 249
 250 #if defined(USE_LZSS_COMPRESSION)
 251 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
 252         if (compressed_bus || store_compressed){                        \
 253             CacheTags<TAGS, LZSSCompression> *tagStore =                \
 254                 new CacheTags<TAGS, LZSSCompression>(tags,              \
 255                                                      compression_latency, \
 256                                                      true, store_compressed, \
 257                                                      adaptive_compression,   \
 258                                                      prefetch_miss); \
 259             BUILD_CACHE(TAGS, LZSSCompression, b, c);                   \
 260         } else {                                                        \
 261             CacheTags<TAGS, NullCompression> *tagStore =                \
 262                 new CacheTags<TAGS, NullCompression>(tags,              \
 263                                                      compression_latency, \
 264                                                      true, store_compressed, \
 265                                                      adaptive_compression,   \
 266                                                      prefetch_miss); \
 267             BUILD_CACHE(TAGS, NullCompression, b, c);                   \
 268         }                                                               \
 269     } while (0)
 270 #else
 271 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
 272         if (compressed_bus || store_compressed){                        \
 273             BUILD_CACHE_PANIC("compressed caches");                     \
 274         } else {                                                        \
 275             CacheTags<TAGS, NullCompression> *tagStore =                \
 276                 new CacheTags<TAGS, NullCompression>(tags,              \
 277                                                       compression_latency, \
 278                                                       true, store_compressed, \
 279                                                       adaptive_compression    \
 280                                                       prefetch_miss); \
 281             BUILD_CACHE(TAGS, NullCompression, b, c);                   \
 282         }                                                               \
 283     } while (0)
 284 #endif
 285
 286 #if defined(USE_CACHE_FALRU)
 287 #define BUILD_FALRU_CACHE(b,c) do {                         \
 288         FALRU *tags = new FALRU(block_size, size, latency); \
 289         BUILD_COMPRESSED_CACHE(FALRU, tags, b, c);              \
 290     } while (0)
 291 #else
 292 #define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
 293 #endif
 294
 295 #if defined(USE_CACHE_LRU)
 296 #define BUILD_LRU_CACHE(b, c) do {                              \
 297         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 298         BUILD_COMPRESSED_CACHE(LRU, tags, b, c);                        \
 299     } while (0)
 300 #else
 301 #define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
 302 #endif
 303
 304 #if defined(USE_CACHE_SPLIT)
 305 #define BUILD_SPLIT_CACHE(b, c) do {                                    \
 306         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
 307                                 two_queue, latency);            \
 308         BUILD_COMPRESSED_CACHE(Split, tags, b, c);                      \
 309     } while (0)
 310 #else
 311 #define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
 312 #endif
 313
 314 #if defined(USE_CACHE_SPLIT_LIFO)
 315 #define BUILD_SPLIT_LIFO_CACHE(b, c) do {                               \
 316         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
 317                                         latency, two_queue, -1);        \
 318         BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c);                  \
 319     } while (0)
 320 #else
 321 #define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
 322 #endif
 323
 324 #if defined(USE_CACHE_IIC)
 325 #define BUILD_IIC_CACHE(b ,c) do {                      \
 326         IIC *tags = new IIC(iic_params);                \
 327         BUILD_COMPRESSED_CACHE(IIC, tags, b, c);        \
 328     } while (0)
 329 #else
 330 #define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
 331 #endif
 332
 333 #define BUILD_CACHES(b, c) do {                         \
 334         if (repl == NULL) {                             \
 335             if (numSets == 1) {                         \
 336                 BUILD_FALRU_CACHE(b, c);                \
 337             } else {                                    \
 338                 if (split == true) {                    \
 339                     BUILD_SPLIT_CACHE(b, c);            \
 340                 } else if (lifo == true) {              \
 341                     BUILD_SPLIT_LIFO_CACHE(b, c);       \
 342                 } else {                                \
 343                     BUILD_LRU_CACHE(b, c);              \
 344                 }                                       \
 345             }                                           \
 346         } else {                                        \
 347             BUILD_IIC_CACHE(b, c);                      \
 348         }                                               \
 349     } while (0)
 350
 351 #define BUILD_COHERENCE(b) do {                                         \
 352         if (protocol == NULL) {                                         \
 353             UniCoherence *coh = new UniCoherence();                     \
 354             BUILD_CACHES(b, UniCoherence);                              \
 355         } else {                                                        \
 356             SimpleCoherence *coh = new SimpleCoherence(protocol);       \
 357             BUILD_CACHES(b, SimpleCoherence);                           \
 358         }                                                               \
 359     } while (0)
 360
 361 #if defined(USE_TAGGED)
 362 #define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new   \
 363                 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 364                                                         !prefetch_past_page, \
 365                                                         prefetch_serial_squash, \
 366                                                         prefetch_cache_check_push, \
 367                                                         prefetch_data_accesses_only, \
 368                                                         prefetch_latency, \
 369                                                         prefetch_degree)
 370 #else
 371 #define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
 372 #endif
 373
 374 #if defined(USE_STRIDED)
 375 #define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new  \
 376                 StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 377                                                         !prefetch_past_page, \
 378                                                         prefetch_serial_squash, \
 379                                                         prefetch_cache_check_push, \
 380                                                         prefetch_data_accesses_only, \
 381                                                         prefetch_latency, \
 382                                                         prefetch_degree, \
 383                                                         prefetch_use_cpu_id)
 384 #else
 385 #define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
 386 #endif
 387
 388 #if defined(USE_GHB)
 389 #define BUILD_GHB_PREFETCHER(t, comp, b) pf = new  \
 390                 GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 391                                                      !prefetch_past_page, \
 392                                                      prefetch_serial_squash, \
 393                                                      prefetch_cache_check_push, \
 394                                                         prefetch_data_accesses_only, \
 395                                                      prefetch_latency, \
 396                                                      prefetch_degree, \
 397                                                      prefetch_use_cpu_id)
 398 #else
 399 #define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
 400 #endif
 401
 402 #if defined(USE_TAGGED)
 403 #define BUILD_NULL_PREFETCHER(t, comp, b) pf = new  \
 404                 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 405                                                         !prefetch_past_page, \
 406                                                         prefetch_serial_squash, \
 407                                                         prefetch_cache_check_push, \
 408                                                         prefetch_data_accesses_only, \
 409                                                         prefetch_latency, \
 410                                                         prefetch_degree)
 411 #else
 412 #define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 413 #endif
 414
 415 CREATE_SIM_OBJECT(BaseCache)
 416 {
 417     string name = getInstanceName();
 418     int numSets = size / (assoc * block_size);
 419     string pf_policy = prefetch_policy;
 420     if (subblock_size == 0) {
 421         subblock_size = block_size;
 422     }
 423
 424     // Build BaseCache param object
 425     BaseCache::Params base_params(addr_range, latency,
 426                                   block_size, max_miss_count);
 427
 428     //Warnings about prefetcher policy
 429     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
 430         panic("With no prefetcher, you shouldn't prefetch from"
 431               " either miss or access stream\n");
 432     }
 433     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 434          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
 435         warn("With this prefetcher you should chose a prefetch"
 436              " stream (miss or access)\nNo Prefetching will occur\n");
 437     }
 438     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 439          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
 440         panic("Can't do prefetches from both miss and access"
 441               " stream\n");
 442     }
 443     if (pf_policy != "tagged" && pf_policy != "stride" &&
 444         pf_policy != "ghb"    && pf_policy != "none") {
 445         panic("Unrecognized form of a prefetcher: %s, try using"
 446               "['none','stride','tagged','ghb']\n", pf_policy);
 447     }
 448
 449 #if defined(USE_CACHE_IIC)
 450     // Build IIC params
 451     IIC::Params iic_params;
 452     iic_params.size = size;
 453     iic_params.numSets = numSets;
 454     iic_params.blkSize = block_size;
 455     iic_params.assoc = assoc;
 456     iic_params.hashDelay = hash_delay;
 457     iic_params.hitLatency = latency;
 458     iic_params.rp = repl;
 459     iic_params.subblockSize = subblock_size;
 460 #else
 461     const void *repl = NULL;
 462 #endif
 463
 464     if (mshrs == 1 /*|| out_bus->doEvents() == false*/) {
 465         BlockingBuffer *mq = new BlockingBuffer(true);
 466         BUILD_COHERENCE(BlockingBuffer);
 467     } else {
 468         MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
 469                                       true, prefetch_miss);
 470         BUILD_COHERENCE(MissQueue);
 471     }
 472     return NULL;
 473 }
 474
 475 REGISTER_SIM_OBJECT("BaseCache", BaseCache)
 476
 477
 478 #endif //DOXYGEN_SHOULD_SKIP_THIS