src/mem/cache/cache_builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "mem/config/cache.hh"
  40 #include "mem/config/prefetch.hh"
  41
  42 #include "mem/cache/base_cache.hh"
  43 #include "mem/cache/cache.hh"
  44 #include "mem/bus.hh"
  45 #include "mem/cache/coherence/coherence_protocol.hh"
  46 #include "sim/builder.hh"
  47
  48 // Tag Templates
  49 #if defined(USE_CACHE_LRU)
  50 #include "mem/cache/tags/lru.hh"
  51 #endif
  52
  53 #if defined(USE_CACHE_FALRU)
  54 #include "mem/cache/tags/fa_lru.hh"
  55 #endif
  56
  57 #if defined(USE_CACHE_IIC)
  58 #include "mem/cache/tags/iic.hh"
  59 #endif
  60
  61 #if defined(USE_CACHE_SPLIT)
  62 #include "mem/cache/tags/split.hh"
  63 #endif
  64
  65 #if defined(USE_CACHE_SPLIT_LIFO)
  66 #include "mem/cache/tags/split_lifo.hh"
  67 #endif
  68
  69 // Compression Templates
  70 #include "base/compression/null_compression.hh"
  71 #include "base/compression/lzss_compression.hh"
  72
  73 // MissQueue Templates
  74 #include "mem/cache/miss/miss_queue.hh"
  75 #include "mem/cache/miss/blocking_buffer.hh"
  76
  77 // Coherence Templates
  78 #include "mem/cache/coherence/uni_coherence.hh"
  79 #include "mem/cache/coherence/simple_coherence.hh"
  80
  81 //Prefetcher Headers
  82 #if defined(USE_GHB)
  83 #include "mem/cache/prefetch/ghb_prefetcher.hh"
  84 #endif
  85 #if defined(USE_TAGGED)
  86 #include "mem/cache/prefetch/tagged_prefetcher.hh"
  87 #endif
  88 #if defined(USE_STRIDED)
  89 #include "mem/cache/prefetch/stride_prefetcher.hh"
  90 #endif
  91
  92
  93 using namespace std;
  94 using namespace TheISA;
  95
  96 #ifndef DOXYGEN_SHOULD_SKIP_THIS
  97
  98 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
  99
 100     Param<int> size;
 101     Param<int> assoc;
 102     Param<int> block_size;
 103     Param<int> latency;
 104     Param<int> mshrs;
 105     Param<int> tgts_per_mshr;
 106     Param<int> write_buffers;
 107     Param<bool> prioritizeRequests;
 108     SimObjectParam<CoherenceProtocol *> protocol;
 109     Param<Addr> trace_addr;
 110     Param<int> hash_delay;
 111 #if defined(USE_CACHE_IIC)
 112     SimObjectParam<Repl *> repl;
 113 #endif
 114     Param<bool> compressed_bus;
 115     Param<bool> store_compressed;
 116     Param<bool> adaptive_compression;
 117     Param<int> compression_latency;
 118     Param<int> subblock_size;
 119     Param<Counter> max_miss_count;
 120     VectorParam<Range<Addr> > addr_range;
 121 //    SimObjectParam<MemTraceWriter *> mem_trace;
 122     Param<bool> split;
 123     Param<int> split_size;
 124     Param<bool> lifo;
 125     Param<bool> two_queue;
 126     Param<bool> prefetch_miss;
 127     Param<bool> prefetch_access;
 128     Param<int> prefetcher_size;
 129     Param<bool> prefetch_past_page;
 130     Param<bool> prefetch_serial_squash;
 131     Param<Tick> prefetch_latency;
 132     Param<int> prefetch_degree;
 133     Param<string> prefetch_policy;
 134     Param<bool> prefetch_cache_check_push;
 135     Param<bool> prefetch_use_cpu_id;
 136     Param<bool> prefetch_data_accesses_only;
 137     Param<int> hit_latency;
 138
 139 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 140
 141
 142 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
 143
 144     INIT_PARAM(size, "capacity in bytes"),
 145     INIT_PARAM(assoc, "associativity"),
 146     INIT_PARAM(block_size, "block size in bytes"),
 147     INIT_PARAM(latency, "hit latency in CPU cycles"),
 148     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
 149     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
 150     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
 151     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
 152                     false),
 153     INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
 154     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 155
 156     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
 157 #if defined(USE_CACHE_IIC)
 158     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
 159 #endif
 160     INIT_PARAM_DFLT(compressed_bus,
 161                     "This cache connects to a compressed memory",
 162                     false),
 163     INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
 164                     false),
 165     INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
 166                     false),
 167     INIT_PARAM_DFLT(compression_latency,
 168                     "Latency in cycles of compression algorithm",
 169                     0),
 170     INIT_PARAM_DFLT(subblock_size,
 171                     "Size of subblock in IIC used for compression",
 172                     0),
 173     INIT_PARAM_DFLT(max_miss_count,
 174                     "The number of misses to handle before calling exit",
 175                     0),
 176     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
 177                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
 178 //    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
 179     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
 180     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
 181     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
 182     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
 183     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
 184     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
 185     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
 186     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
 187     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
 188     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
 189     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
 190     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
 191     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
 192     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
 193     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false),
 194     INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1)
 195 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 196
 197
 198 #define BUILD_CACHE(TAGS, tags, c)                                      \
 199     do {                                                                \
 200         BasePrefetcher *pf;                                           \
 201         if (pf_policy == "tagged") {                                    \
 202             BUILD_TAGGED_PREFETCHER(TAGS);                              \
 203         }                                                               \
 204         else if (pf_policy == "stride") {                               \
 205             BUILD_STRIDED_PREFETCHER(TAGS);                             \
 206         }                                                               \
 207         else if (pf_policy == "ghb") {                                  \
 208             BUILD_GHB_PREFETCHER(TAGS);                                 \
 209         }                                                               \
 210         else {                                                          \
 211             BUILD_NULL_PREFETCHER(TAGS);                                \
 212         }                                                               \
 213         Cache<TAGS, c>::Params params(tags, mq, coh, base_params,       \
 214                                       pf, prefetch_access, hit_latency, \
 215                                       true,                             \
 216                                       store_compressed,                 \
 217                                       adaptive_compression,             \
 218                                       compressed_bus,                   \
 219                                       compAlg, compression_latency,     \
 220                                       prefetch_miss);                   \
 221         Cache<TAGS, c> *retval =                                        \
 222             new Cache<TAGS, c>(getInstanceName(), params);              \
 223         return retval;                                                  \
 224     } while (0)
 225
 226 #define BUILD_CACHE_PANIC(x) do {                       \
 227         panic("%s not compiled into M5", x);            \
 228     } while (0)
 229
 230 #define BUILD_COMPRESSED_CACHE(TAGS, tags, c)           \
 231     do {                                                \
 232         CompressionAlgorithm *compAlg;                  \
 233         if (compressed_bus || store_compressed) {       \
 234             compAlg = new LZSSCompression();            \
 235         } else {                                        \
 236             compAlg = new NullCompression();            \
 237         }                                               \
 238         BUILD_CACHE(TAGS, tags, c);                     \
 239     } while (0)
 240
 241 #if defined(USE_CACHE_FALRU)
 242 #define BUILD_FALRU_CACHE(c) do {                           \
 243         FALRU *tags = new FALRU(block_size, size, latency); \
 244         BUILD_COMPRESSED_CACHE(FALRU, tags, c);         \
 245     } while (0)
 246 #else
 247 #define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
 248 #endif
 249
 250 #if defined(USE_CACHE_LRU)
 251 #define BUILD_LRU_CACHE(c) do {                         \
 252         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 253         BUILD_COMPRESSED_CACHE(LRU, tags, c);                   \
 254     } while (0)
 255 #else
 256 #define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
 257 #endif
 258
 259 #if defined(USE_CACHE_SPLIT)
 260 #define BUILD_SPLIT_CACHE(c) do {                                       \
 261         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
 262                                 two_queue, latency);            \
 263         BUILD_COMPRESSED_CACHE(Split, tags, c);                 \
 264     } while (0)
 265 #else
 266 #define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
 267 #endif
 268
 269 #if defined(USE_CACHE_SPLIT_LIFO)
 270 #define BUILD_SPLIT_LIFO_CACHE(c) do {                          \
 271         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
 272                                         latency, two_queue, -1);        \
 273         BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c);                     \
 274     } while (0)
 275 #else
 276 #define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
 277 #endif
 278
 279 #if defined(USE_CACHE_IIC)
 280 #define BUILD_IIC_CACHE(c) do {                 \
 281         IIC *tags = new IIC(iic_params);                \
 282         BUILD_COMPRESSED_CACHE(IIC, tags, c);   \
 283     } while (0)
 284 #else
 285 #define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
 286 #endif
 287
 288 #define BUILD_CACHES(c) do {                            \
 289         if (repl == NULL) {                             \
 290             if (numSets == 1) {                         \
 291                 BUILD_FALRU_CACHE(c);           \
 292             } else {                                    \
 293                 if (split == true) {                    \
 294                     BUILD_SPLIT_CACHE(c);               \
 295                 } else if (lifo == true) {              \
 296                     BUILD_SPLIT_LIFO_CACHE(c);  \
 297                 } else {                                \
 298                     BUILD_LRU_CACHE(c);         \
 299                 }                                       \
 300             }                                           \
 301         } else {                                        \
 302             BUILD_IIC_CACHE(c);                 \
 303         }                                               \
 304     } while (0)
 305
 306 #define BUILD_COHERENCE(b) do {                                         \
 307         if (protocol == NULL) {                                         \
 308             UniCoherence *coh = new UniCoherence();                     \
 309             BUILD_CACHES(UniCoherence);                         \
 310         } else {                                                        \
 311             SimpleCoherence *coh = new SimpleCoherence(protocol);       \
 312             BUILD_CACHES(SimpleCoherence);                              \
 313         }                                                               \
 314     } while (0)
 315
 316 #if defined(USE_TAGGED)
 317 #define BUILD_TAGGED_PREFETCHER(t)                              \
 318     pf = new TaggedPrefetcher(prefetcher_size,                  \
 319                               !prefetch_past_page,              \
 320                               prefetch_serial_squash,           \
 321                               prefetch_cache_check_push,        \
 322                               prefetch_data_accesses_only,      \
 323                               prefetch_latency,                 \
 324                               prefetch_degree)
 325 #else
 326 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 327 #endif
 328
 329 #if defined(USE_STRIDED)
 330 #define BUILD_STRIDED_PREFETCHER(t)                             \
 331     pf = new StridePrefetcher(prefetcher_size,                  \
 332                               !prefetch_past_page,              \
 333                               prefetch_serial_squash,           \
 334                               prefetch_cache_check_push,        \
 335                               prefetch_data_accesses_only,      \
 336                               prefetch_latency,                 \
 337                               prefetch_degree,                  \
 338                               prefetch_use_cpu_id)
 339 #else
 340 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 341 #endif
 342
 343 #if defined(USE_GHB)
 344 #define BUILD_GHB_PREFETCHER(t)                         \
 345     pf = new GHBPrefetcher(prefetcher_size,             \
 346                            !prefetch_past_page,         \
 347                            prefetch_serial_squash,      \
 348                            prefetch_cache_check_push,   \
 349                            prefetch_data_accesses_only, \
 350                            prefetch_latency,            \
 351                            prefetch_degree,             \
 352                            prefetch_use_cpu_id)
 353 #else
 354 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 355 #endif
 356
 357 #if defined(USE_TAGGED)
 358 #define BUILD_NULL_PREFETCHER(t)                                \
 359     pf = new TaggedPrefetcher(prefetcher_size,                  \
 360                               !prefetch_past_page,              \
 361                               prefetch_serial_squash,           \
 362                               prefetch_cache_check_push,        \
 363                               prefetch_data_accesses_only,      \
 364                               prefetch_latency,                 \
 365                               prefetch_degree)
 366 #else
 367 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 368 #endif
 369
 370 CREATE_SIM_OBJECT(BaseCache)
 371 {
 372     string name = getInstanceName();
 373     int numSets = size / (assoc * block_size);
 374     string pf_policy = prefetch_policy;
 375     if (subblock_size == 0) {
 376         subblock_size = block_size;
 377     }
 378
 379     // Build BaseCache param object
 380     BaseCache::Params base_params(addr_range, latency,
 381                                   block_size, max_miss_count);
 382
 383     //Warnings about prefetcher policy
 384     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
 385         panic("With no prefetcher, you shouldn't prefetch from"
 386               " either miss or access stream\n");
 387     }
 388     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 389          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
 390         warn("With this prefetcher you should chose a prefetch"
 391              " stream (miss or access)\nNo Prefetching will occur\n");
 392     }
 393     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 394          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
 395         panic("Can't do prefetches from both miss and access"
 396               " stream\n");
 397     }
 398     if (pf_policy != "tagged" && pf_policy != "stride" &&
 399         pf_policy != "ghb"    && pf_policy != "none") {
 400         panic("Unrecognized form of a prefetcher: %s, try using"
 401               "['none','stride','tagged','ghb']\n", pf_policy);
 402     }
 403
 404 #if defined(USE_CACHE_IIC)
 405     // Build IIC params
 406     IIC::Params iic_params;
 407     iic_params.size = size;
 408     iic_params.numSets = numSets;
 409     iic_params.blkSize = block_size;
 410     iic_params.assoc = assoc;
 411     iic_params.hashDelay = hash_delay;
 412     iic_params.hitLatency = latency;
 413     iic_params.rp = repl;
 414     iic_params.subblockSize = subblock_size;
 415 #else
 416     const void *repl = NULL;
 417 #endif
 418
 419     if (mshrs == 1 /*|| out_bus->doEvents() == false*/) {
 420         BlockingBuffer *mq = new BlockingBuffer(true);
 421         BUILD_COHERENCE(BlockingBuffer);
 422     } else {
 423         MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
 424                                       true, prefetch_miss);
 425         BUILD_COHERENCE(MissQueue);
 426     }
 427     return NULL;
 428 }
 429
 430 REGISTER_SIM_OBJECT("BaseCache", BaseCache)
 431
 432
 433 #endif //DOXYGEN_SHOULD_SKIP_THIS