src/mem/cache/cache_builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "mem/config/cache.hh"
  40 #include "mem/config/prefetch.hh"
  41
  42 #include "mem/cache/base_cache.hh"
  43 #include "mem/cache/cache.hh"
  44 #include "mem/bus.hh"
  45 #include "sim/builder.hh"
  46
  47 // Tag Templates
  48 #if defined(USE_CACHE_LRU)
  49 #include "mem/cache/tags/lru.hh"
  50 #endif
  51
  52 #if defined(USE_CACHE_FALRU)
  53 #include "mem/cache/tags/fa_lru.hh"
  54 #endif
  55
  56 #if defined(USE_CACHE_IIC)
  57 #include "mem/cache/tags/iic.hh"
  58 #endif
  59
  60 #if defined(USE_CACHE_SPLIT)
  61 #include "mem/cache/tags/split.hh"
  62 #endif
  63
  64 #if defined(USE_CACHE_SPLIT_LIFO)
  65 #include "mem/cache/tags/split_lifo.hh"
  66 #endif
  67
  68 //Prefetcher Headers
  69 #if defined(USE_GHB)
  70 #include "mem/cache/prefetch/ghb_prefetcher.hh"
  71 #endif
  72 #if defined(USE_TAGGED)
  73 #include "mem/cache/prefetch/tagged_prefetcher.hh"
  74 #endif
  75 #if defined(USE_STRIDED)
  76 #include "mem/cache/prefetch/stride_prefetcher.hh"
  77 #endif
  78
  79
  80 using namespace std;
  81 using namespace TheISA;
  82
  83 #ifndef DOXYGEN_SHOULD_SKIP_THIS
  84
  85 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
  86
  87     Param<int> size;
  88     Param<int> assoc;
  89     Param<int> block_size;
  90     Param<int> latency;
  91     Param<int> mshrs;
  92     Param<int> tgts_per_mshr;
  93     Param<int> write_buffers;
  94     Param<bool> prioritizeRequests;
  95     Param<Addr> trace_addr;
  96     Param<int> hash_delay;
  97 #if defined(USE_CACHE_IIC)
  98     SimObjectParam<Repl *> repl;
  99 #endif
 100     Param<int> subblock_size;
 101     Param<Counter> max_miss_count;
 102     VectorParam<Range<Addr> > addr_range;
 103 //    SimObjectParam<MemTraceWriter *> mem_trace;
 104     Param<bool> split;
 105     Param<int> split_size;
 106     Param<bool> lifo;
 107     Param<bool> two_queue;
 108     Param<bool> prefetch_miss;
 109     Param<bool> prefetch_access;
 110     Param<int> prefetcher_size;
 111     Param<bool> prefetch_past_page;
 112     Param<bool> prefetch_serial_squash;
 113     Param<Tick> prefetch_latency;
 114     Param<int> prefetch_degree;
 115     Param<string> prefetch_policy;
 116     Param<bool> prefetch_cache_check_push;
 117     Param<bool> prefetch_use_cpu_id;
 118     Param<bool> prefetch_data_accesses_only;
 119
 120 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 121
 122
 123 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
 124
 125     INIT_PARAM(size, "capacity in bytes"),
 126     INIT_PARAM(assoc, "associativity"),
 127     INIT_PARAM(block_size, "block size in bytes"),
 128     INIT_PARAM(latency, "hit latency in CPU cycles"),
 129     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
 130     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
 131     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
 132     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
 133                     false),
 134     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 135
 136     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
 137 #if defined(USE_CACHE_IIC)
 138     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
 139 #endif
 140     INIT_PARAM_DFLT(subblock_size,
 141                     "Size of subblock in IIC used for compression",
 142                     0),
 143     INIT_PARAM_DFLT(max_miss_count,
 144                     "The number of misses to handle before calling exit",
 145                     0),
 146     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
 147                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
 148 //    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
 149     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
 150     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
 151     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
 152     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
 153     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
 154     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
 155     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
 156     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
 157     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
 158     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
 159     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
 160     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
 161     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
 162     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
 163     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
 164 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 165
 166
 167 #define BUILD_CACHE(TAGS, tags)                                      \
 168     do {                                                                \
 169         BasePrefetcher *pf;                                           \
 170         if (pf_policy == "tagged") {                                    \
 171             BUILD_TAGGED_PREFETCHER(TAGS);                              \
 172         }                                                               \
 173         else if (pf_policy == "stride") {                               \
 174             BUILD_STRIDED_PREFETCHER(TAGS);                             \
 175         }                                                               \
 176         else if (pf_policy == "ghb") {                                  \
 177             BUILD_GHB_PREFETCHER(TAGS);                                 \
 178         }                                                               \
 179         else {                                                          \
 180             BUILD_NULL_PREFETCHER(TAGS);                                \
 181         }                                                               \
 182         Cache<TAGS>::Params params(tags, base_params,       \
 183                                    pf, prefetch_access, latency,        \
 184                                    true,                                \
 185                                    prefetch_miss);                      \
 186         Cache<TAGS> *retval =                                        \
 187             new Cache<TAGS>(getInstanceName(), params);              \
 188         return retval;                                                  \
 189     } while (0)
 190
 191 #define BUILD_CACHE_PANIC(x) do {                       \
 192         panic("%s not compiled into M5", x);            \
 193     } while (0)
 194
 195 #if defined(USE_CACHE_FALRU)
 196 #define BUILD_FALRU_CACHE do {                      \
 197         FALRU *tags = new FALRU(block_size, size, latency); \
 198         BUILD_CACHE(FALRU, tags);               \
 199     } while (0)
 200 #else
 201 #define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
 202 #endif
 203
 204 #if defined(USE_CACHE_LRU)
 205 #define BUILD_LRU_CACHE do {                            \
 206         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 207         BUILD_CACHE(LRU, tags);                 \
 208     } while (0)
 209 #else
 210 #define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
 211 #endif
 212
 213 #if defined(USE_CACHE_SPLIT)
 214 #define BUILD_SPLIT_CACHE do {                                  \
 215         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
 216                                 two_queue, latency);            \
 217         BUILD_CACHE(Split, tags);                       \
 218     } while (0)
 219 #else
 220 #define BUILD_SPLIT_CACHE BUILD_CACHE_PANIC("split cache")
 221 #endif
 222
 223 #if defined(USE_CACHE_SPLIT_LIFO)
 224 #define BUILD_SPLIT_LIFO_CACHE do {                             \
 225         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
 226                                         latency, two_queue, -1);        \
 227         BUILD_CACHE(SplitLIFO, tags);                   \
 228     } while (0)
 229 #else
 230 #define BUILD_SPLIT_LIFO_CACHE BUILD_CACHE_PANIC("lifo cache")
 231 #endif
 232
 233 #if defined(USE_CACHE_IIC)
 234 #define BUILD_IIC_CACHE do {                    \
 235         IIC *tags = new IIC(iic_params);                \
 236         BUILD_CACHE(IIC, tags); \
 237     } while (0)
 238 #else
 239 #define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
 240 #endif
 241
 242 #define BUILD_CACHES do {                               \
 243         if (repl == NULL) {                             \
 244             if (numSets == 1) {                         \
 245                 BUILD_FALRU_CACHE;              \
 246             } else {                                    \
 247                 if (split == true) {                    \
 248                     BUILD_SPLIT_CACHE;          \
 249                 } else if (lifo == true) {              \
 250                     BUILD_SPLIT_LIFO_CACHE;     \
 251                 } else {                                \
 252                     BUILD_LRU_CACHE;            \
 253                 }                                       \
 254             }                                           \
 255         } else {                                        \
 256             BUILD_IIC_CACHE;                    \
 257         }                                               \
 258     } while (0)
 259
 260 #define BUILD_COHERENCE(b) do {                                         \
 261     } while (0)
 262
 263 #if defined(USE_TAGGED)
 264 #define BUILD_TAGGED_PREFETCHER(t)                              \
 265     pf = new TaggedPrefetcher(prefetcher_size,                  \
 266                               !prefetch_past_page,              \
 267                               prefetch_serial_squash,           \
 268                               prefetch_cache_check_push,        \
 269                               prefetch_data_accesses_only,      \
 270                               prefetch_latency,                 \
 271                               prefetch_degree)
 272 #else
 273 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 274 #endif
 275
 276 #if defined(USE_STRIDED)
 277 #define BUILD_STRIDED_PREFETCHER(t)                             \
 278     pf = new StridePrefetcher(prefetcher_size,                  \
 279                               !prefetch_past_page,              \
 280                               prefetch_serial_squash,           \
 281                               prefetch_cache_check_push,        \
 282                               prefetch_data_accesses_only,      \
 283                               prefetch_latency,                 \
 284                               prefetch_degree,                  \
 285                               prefetch_use_cpu_id)
 286 #else
 287 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 288 #endif
 289
 290 #if defined(USE_GHB)
 291 #define BUILD_GHB_PREFETCHER(t)                         \
 292     pf = new GHBPrefetcher(prefetcher_size,             \
 293                            !prefetch_past_page,         \
 294                            prefetch_serial_squash,      \
 295                            prefetch_cache_check_push,   \
 296                            prefetch_data_accesses_only, \
 297                            prefetch_latency,            \
 298                            prefetch_degree,             \
 299                            prefetch_use_cpu_id)
 300 #else
 301 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 302 #endif
 303
 304 #if defined(USE_TAGGED)
 305 #define BUILD_NULL_PREFETCHER(t)                                \
 306     pf = new TaggedPrefetcher(prefetcher_size,                  \
 307                               !prefetch_past_page,              \
 308                               prefetch_serial_squash,           \
 309                               prefetch_cache_check_push,        \
 310                               prefetch_data_accesses_only,      \
 311                               prefetch_latency,                 \
 312                               prefetch_degree)
 313 #else
 314 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 315 #endif
 316
 317 CREATE_SIM_OBJECT(BaseCache)
 318 {
 319     string name = getInstanceName();
 320     int numSets = size / (assoc * block_size);
 321     string pf_policy = prefetch_policy;
 322     if (subblock_size == 0) {
 323         subblock_size = block_size;
 324     }
 325
 326     // Build BaseCache param object
 327     BaseCache::Params base_params(latency, block_size,
 328                                   mshrs, tgts_per_mshr, write_buffers,
 329                                   max_miss_count);
 330
 331     //Warnings about prefetcher policy
 332     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
 333         panic("With no prefetcher, you shouldn't prefetch from"
 334               " either miss or access stream\n");
 335     }
 336     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 337          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
 338         warn("With this prefetcher you should chose a prefetch"
 339              " stream (miss or access)\nNo Prefetching will occur\n");
 340     }
 341     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 342          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
 343         panic("Can't do prefetches from both miss and access"
 344               " stream\n");
 345     }
 346     if (pf_policy != "tagged" && pf_policy != "stride" &&
 347         pf_policy != "ghb"    && pf_policy != "none") {
 348         panic("Unrecognized form of a prefetcher: %s, try using"
 349               "['none','stride','tagged','ghb']\n", pf_policy);
 350     }
 351
 352 #if defined(USE_CACHE_IIC)
 353     // Build IIC params
 354     IIC::Params iic_params;
 355     iic_params.size = size;
 356     iic_params.numSets = numSets;
 357     iic_params.blkSize = block_size;
 358     iic_params.assoc = assoc;
 359     iic_params.hashDelay = hash_delay;
 360     iic_params.hitLatency = latency;
 361     iic_params.rp = repl;
 362     iic_params.subblockSize = subblock_size;
 363 #else
 364     const void *repl = NULL;
 365 #endif
 366
 367     BUILD_CACHES;
 368     return NULL;
 369 }
 370
 371 REGISTER_SIM_OBJECT("BaseCache", BaseCache)
 372
 373
 374 #endif //DOXYGEN_SHOULD_SKIP_THIS