src/mem/cache/cache_builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "mem/config/cache.hh"
  40 #include "mem/config/prefetch.hh"
  41
  42 #include "mem/cache/base_cache.hh"
  43 #include "mem/cache/cache.hh"
  44 #include "mem/bus.hh"
  45 #include "mem/cache/coherence/coherence_protocol.hh"
  46 #include "sim/builder.hh"
  47
  48 // Tag Templates
  49 #if defined(USE_CACHE_LRU)
  50 #include "mem/cache/tags/lru.hh"
  51 #endif
  52
  53 #if defined(USE_CACHE_FALRU)
  54 #include "mem/cache/tags/fa_lru.hh"
  55 #endif
  56
  57 #if defined(USE_CACHE_IIC)
  58 #include "mem/cache/tags/iic.hh"
  59 #endif
  60
  61 #if defined(USE_CACHE_SPLIT)
  62 #include "mem/cache/tags/split.hh"
  63 #endif
  64
  65 #if defined(USE_CACHE_SPLIT_LIFO)
  66 #include "mem/cache/tags/split_lifo.hh"
  67 #endif
  68
  69 // Compression Templates
  70 #include "base/compression/null_compression.hh"
  71 #include "base/compression/lzss_compression.hh"
  72
  73 // MissQueue Templates
  74 #include "mem/cache/miss/miss_queue.hh"
  75 #include "mem/cache/miss/blocking_buffer.hh"
  76
  77 // Coherence Templates
  78 #include "mem/cache/coherence/uni_coherence.hh"
  79 #include "mem/cache/coherence/simple_coherence.hh"
  80
  81 //Prefetcher Headers
  82 #if defined(USE_GHB)
  83 #include "mem/cache/prefetch/ghb_prefetcher.hh"
  84 #endif
  85 #if defined(USE_TAGGED)
  86 #include "mem/cache/prefetch/tagged_prefetcher.hh"
  87 #endif
  88 #if defined(USE_STRIDED)
  89 #include "mem/cache/prefetch/stride_prefetcher.hh"
  90 #endif
  91
  92
  93 using namespace std;
  94 using namespace TheISA;
  95
  96 #ifndef DOXYGEN_SHOULD_SKIP_THIS
  97
  98 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
  99
 100     Param<int> size;
 101     Param<int> assoc;
 102     Param<int> block_size;
 103     Param<int> latency;
 104     Param<int> mshrs;
 105     Param<int> tgts_per_mshr;
 106     Param<int> write_buffers;
 107     Param<bool> prioritizeRequests;
 108     SimObjectParam<CoherenceProtocol *> protocol;
 109     Param<Addr> trace_addr;
 110     Param<int> hash_delay;
 111 #if defined(USE_CACHE_IIC)
 112     SimObjectParam<Repl *> repl;
 113 #endif
 114     Param<bool> compressed_bus;
 115     Param<bool> store_compressed;
 116     Param<bool> adaptive_compression;
 117     Param<int> compression_latency;
 118     Param<int> subblock_size;
 119     Param<Counter> max_miss_count;
 120     VectorParam<Range<Addr> > addr_range;
 121 //    SimObjectParam<MemTraceWriter *> mem_trace;
 122     Param<bool> split;
 123     Param<int> split_size;
 124     Param<bool> lifo;
 125     Param<bool> two_queue;
 126     Param<bool> prefetch_miss;
 127     Param<bool> prefetch_access;
 128     Param<int> prefetcher_size;
 129     Param<bool> prefetch_past_page;
 130     Param<bool> prefetch_serial_squash;
 131     Param<Tick> prefetch_latency;
 132     Param<int> prefetch_degree;
 133     Param<string> prefetch_policy;
 134     Param<bool> prefetch_cache_check_push;
 135     Param<bool> prefetch_use_cpu_id;
 136     Param<bool> prefetch_data_accesses_only;
 137
 138 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 139
 140
 141 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
 142
 143     INIT_PARAM(size, "capacity in bytes"),
 144     INIT_PARAM(assoc, "associativity"),
 145     INIT_PARAM(block_size, "block size in bytes"),
 146     INIT_PARAM(latency, "hit latency in CPU cycles"),
 147     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
 148     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
 149     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
 150     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
 151                     false),
 152     INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
 153     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 154
 155     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
 156 #if defined(USE_CACHE_IIC)
 157     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
 158 #endif
 159     INIT_PARAM_DFLT(compressed_bus,
 160                     "This cache connects to a compressed memory",
 161                     false),
 162     INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
 163                     false),
 164     INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
 165                     false),
 166     INIT_PARAM_DFLT(compression_latency,
 167                     "Latency in cycles of compression algorithm",
 168                     0),
 169     INIT_PARAM_DFLT(subblock_size,
 170                     "Size of subblock in IIC used for compression",
 171                     0),
 172     INIT_PARAM_DFLT(max_miss_count,
 173                     "The number of misses to handle before calling exit",
 174                     0),
 175     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
 176                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
 177 //    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
 178     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
 179     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
 180     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
 181     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
 182     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
 183     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
 184     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
 185     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
 186     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
 187     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
 188     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
 189     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
 190     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
 191     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
 192     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
 193 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 194
 195
 196 #define BUILD_CACHE(TAGS, tags, c)                                      \
 197     do {                                                                \
 198         BasePrefetcher *pf;                                           \
 199         if (pf_policy == "tagged") {                                    \
 200             BUILD_TAGGED_PREFETCHER(TAGS);                              \
 201         }                                                               \
 202         else if (pf_policy == "stride") {                               \
 203             BUILD_STRIDED_PREFETCHER(TAGS);                             \
 204         }                                                               \
 205         else if (pf_policy == "ghb") {                                  \
 206             BUILD_GHB_PREFETCHER(TAGS);                                 \
 207         }                                                               \
 208         else {                                                          \
 209             BUILD_NULL_PREFETCHER(TAGS);                                \
 210         }                                                               \
 211         Cache<TAGS, c>::Params params(tags, mq, coh, base_params,       \
 212                                       pf, prefetch_access, latency, \
 213                                       true,                             \
 214                                       store_compressed,                 \
 215                                       adaptive_compression,             \
 216                                       compressed_bus,                   \
 217                                       compAlg, compression_latency,     \
 218                                       prefetch_miss);                   \
 219         Cache<TAGS, c> *retval =                                        \
 220             new Cache<TAGS, c>(getInstanceName(), params);              \
 221         return retval;                                                  \
 222     } while (0)
 223
 224 #define BUILD_CACHE_PANIC(x) do {                       \
 225         panic("%s not compiled into M5", x);            \
 226     } while (0)
 227
 228 #define BUILD_COMPRESSED_CACHE(TAGS, tags, c)           \
 229     do {                                                \
 230         CompressionAlgorithm *compAlg;                  \
 231         if (compressed_bus || store_compressed) {       \
 232             compAlg = new LZSSCompression();            \
 233         } else {                                        \
 234             compAlg = new NullCompression();            \
 235         }                                               \
 236         BUILD_CACHE(TAGS, tags, c);                     \
 237     } while (0)
 238
 239 #if defined(USE_CACHE_FALRU)
 240 #define BUILD_FALRU_CACHE(c) do {                           \
 241         FALRU *tags = new FALRU(block_size, size, latency); \
 242         BUILD_COMPRESSED_CACHE(FALRU, tags, c);         \
 243     } while (0)
 244 #else
 245 #define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
 246 #endif
 247
 248 #if defined(USE_CACHE_LRU)
 249 #define BUILD_LRU_CACHE(c) do {                         \
 250         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 251         BUILD_COMPRESSED_CACHE(LRU, tags, c);                   \
 252     } while (0)
 253 #else
 254 #define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
 255 #endif
 256
 257 #if defined(USE_CACHE_SPLIT)
 258 #define BUILD_SPLIT_CACHE(c) do {                                       \
 259         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
 260                                 two_queue, latency);            \
 261         BUILD_COMPRESSED_CACHE(Split, tags, c);                 \
 262     } while (0)
 263 #else
 264 #define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
 265 #endif
 266
 267 #if defined(USE_CACHE_SPLIT_LIFO)
 268 #define BUILD_SPLIT_LIFO_CACHE(c) do {                          \
 269         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
 270                                         latency, two_queue, -1);        \
 271         BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c);                     \
 272     } while (0)
 273 #else
 274 #define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
 275 #endif
 276
 277 #if defined(USE_CACHE_IIC)
 278 #define BUILD_IIC_CACHE(c) do {                 \
 279         IIC *tags = new IIC(iic_params);                \
 280         BUILD_COMPRESSED_CACHE(IIC, tags, c);   \
 281     } while (0)
 282 #else
 283 #define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
 284 #endif
 285
 286 #define BUILD_CACHES(c) do {                            \
 287         if (repl == NULL) {                             \
 288             if (numSets == 1) {                         \
 289                 BUILD_FALRU_CACHE(c);           \
 290             } else {                                    \
 291                 if (split == true) {                    \
 292                     BUILD_SPLIT_CACHE(c);               \
 293                 } else if (lifo == true) {              \
 294                     BUILD_SPLIT_LIFO_CACHE(c);  \
 295                 } else {                                \
 296                     BUILD_LRU_CACHE(c);         \
 297                 }                                       \
 298             }                                           \
 299         } else {                                        \
 300             BUILD_IIC_CACHE(c);                 \
 301         }                                               \
 302     } while (0)
 303
 304 #define BUILD_COHERENCE(b) do {                                         \
 305         if (protocol == NULL) {                                         \
 306             UniCoherence *coh = new UniCoherence();                     \
 307             BUILD_CACHES(UniCoherence);                         \
 308         } else {                                                        \
 309             SimpleCoherence *coh = new SimpleCoherence(protocol);       \
 310             BUILD_CACHES(SimpleCoherence);                              \
 311         }                                                               \
 312     } while (0)
 313
 314 #if defined(USE_TAGGED)
 315 #define BUILD_TAGGED_PREFETCHER(t)                              \
 316     pf = new TaggedPrefetcher(prefetcher_size,                  \
 317                               !prefetch_past_page,              \
 318                               prefetch_serial_squash,           \
 319                               prefetch_cache_check_push,        \
 320                               prefetch_data_accesses_only,      \
 321                               prefetch_latency,                 \
 322                               prefetch_degree)
 323 #else
 324 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 325 #endif
 326
 327 #if defined(USE_STRIDED)
 328 #define BUILD_STRIDED_PREFETCHER(t)                             \
 329     pf = new StridePrefetcher(prefetcher_size,                  \
 330                               !prefetch_past_page,              \
 331                               prefetch_serial_squash,           \
 332                               prefetch_cache_check_push,        \
 333                               prefetch_data_accesses_only,      \
 334                               prefetch_latency,                 \
 335                               prefetch_degree,                  \
 336                               prefetch_use_cpu_id)
 337 #else
 338 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 339 #endif
 340
 341 #if defined(USE_GHB)
 342 #define BUILD_GHB_PREFETCHER(t)                         \
 343     pf = new GHBPrefetcher(prefetcher_size,             \
 344                            !prefetch_past_page,         \
 345                            prefetch_serial_squash,      \
 346                            prefetch_cache_check_push,   \
 347                            prefetch_data_accesses_only, \
 348                            prefetch_latency,            \
 349                            prefetch_degree,             \
 350                            prefetch_use_cpu_id)
 351 #else
 352 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 353 #endif
 354
 355 #if defined(USE_TAGGED)
 356 #define BUILD_NULL_PREFETCHER(t)                                \
 357     pf = new TaggedPrefetcher(prefetcher_size,                  \
 358                               !prefetch_past_page,              \
 359                               prefetch_serial_squash,           \
 360                               prefetch_cache_check_push,        \
 361                               prefetch_data_accesses_only,      \
 362                               prefetch_latency,                 \
 363                               prefetch_degree)
 364 #else
 365 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 366 #endif
 367
 368 CREATE_SIM_OBJECT(BaseCache)
 369 {
 370     string name = getInstanceName();
 371     int numSets = size / (assoc * block_size);
 372     string pf_policy = prefetch_policy;
 373     if (subblock_size == 0) {
 374         subblock_size = block_size;
 375     }
 376
 377     // Build BaseCache param object
 378     BaseCache::Params base_params(addr_range, latency,
 379                                   block_size, max_miss_count);
 380
 381     //Warnings about prefetcher policy
 382     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
 383         panic("With no prefetcher, you shouldn't prefetch from"
 384               " either miss or access stream\n");
 385     }
 386     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 387          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
 388         warn("With this prefetcher you should chose a prefetch"
 389              " stream (miss or access)\nNo Prefetching will occur\n");
 390     }
 391     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 392          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
 393         panic("Can't do prefetches from both miss and access"
 394               " stream\n");
 395     }
 396     if (pf_policy != "tagged" && pf_policy != "stride" &&
 397         pf_policy != "ghb"    && pf_policy != "none") {
 398         panic("Unrecognized form of a prefetcher: %s, try using"
 399               "['none','stride','tagged','ghb']\n", pf_policy);
 400     }
 401
 402 #if defined(USE_CACHE_IIC)
 403     // Build IIC params
 404     IIC::Params iic_params;
 405     iic_params.size = size;
 406     iic_params.numSets = numSets;
 407     iic_params.blkSize = block_size;
 408     iic_params.assoc = assoc;
 409     iic_params.hashDelay = hash_delay;
 410     iic_params.hitLatency = latency;
 411     iic_params.rp = repl;
 412     iic_params.subblockSize = subblock_size;
 413 #else
 414     const void *repl = NULL;
 415 #endif
 416
 417     if (mshrs == 1 /*|| out_bus->doEvents() == false*/) {
 418         BlockingBuffer *mq = new BlockingBuffer(true);
 419         BUILD_COHERENCE(BlockingBuffer);
 420     } else {
 421         MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
 422                                       true, prefetch_miss);
 423         BUILD_COHERENCE(MissQueue);
 424     }
 425     return NULL;
 426 }
 427
 428 REGISTER_SIM_OBJECT("BaseCache", BaseCache)
 429
 430
 431 #endif //DOXYGEN_SHOULD_SKIP_THIS