2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
34 * Simobject instatiation of caches.
38 // Must be included first to determine which caches we want
39 #include "mem/config/cache.hh"
40 #include "mem/config/compression.hh"
41 #include "mem/config/prefetch.hh"
43 #include "mem/cache/base_cache.hh"
44 #include "mem/cache/cache.hh"
46 #include "mem/cache/coherence/coherence_protocol.hh"
47 #include "sim/builder.hh"
50 #if defined(USE_CACHE_LRU)
51 #include "mem/cache/tags/lru.hh"
54 #if defined(USE_CACHE_FALRU)
55 #include "mem/cache/tags/fa_lru.hh"
58 #if defined(USE_CACHE_IIC)
59 #include "mem/cache/tags/iic.hh"
62 #if defined(USE_CACHE_SPLIT)
63 #include "mem/cache/tags/split.hh"
66 #if defined(USE_CACHE_SPLIT_LIFO)
67 #include "mem/cache/tags/split_lifo.hh"
70 // Compression Templates
71 #include "base/compression/null_compression.hh"
72 #if defined(USE_LZSS_COMPRESSION)
73 #include "base/compression/lzss_compression.hh"
76 // CacheTags Templates
77 #include "mem/cache/tags/cache_tags.hh"
79 // MissQueue Templates
80 #include "mem/cache/miss/miss_queue.hh"
81 #include "mem/cache/miss/blocking_buffer.hh"
83 // Coherence Templates
84 #include "mem/cache/coherence/uni_coherence.hh"
85 #include "mem/cache/coherence/simple_coherence.hh"
89 #include "mem/cache/prefetch/ghb_prefetcher.hh"
91 #if defined(USE_TAGGED)
92 #include "mem/cache/prefetch/tagged_prefetcher.hh"
94 #if defined(USE_STRIDED)
95 #include "mem/cache/prefetch/stride_prefetcher.hh"
100 using namespace TheISA
;
102 #ifndef DOXYGEN_SHOULD_SKIP_THIS
104 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache
)
108 Param
<int> block_size
;
111 Param
<int> tgts_per_mshr
;
112 Param
<int> write_buffers
;
113 Param
<bool> prioritizeRequests
;
114 // SimObjectParam<Bus *> in_bus;
115 // SimObjectParam<Bus *> out_bus;
116 SimObjectParam
<CoherenceProtocol
*> protocol
;
117 Param
<Addr
> trace_addr
;
118 Param
<int> hash_delay
;
119 #if defined(USE_CACHE_IIC)
120 SimObjectParam
<Repl
*> repl
;
122 Param
<bool> compressed_bus
;
123 Param
<bool> store_compressed
;
124 Param
<bool> adaptive_compression
;
125 Param
<int> compression_latency
;
126 Param
<int> subblock_size
;
127 Param
<Counter
> max_miss_count
;
128 // SimObjectParam<HierParams *> hier;
129 VectorParam
<Range
<Addr
> > addr_range
;
130 // SimObjectParam<MemTraceWriter *> mem_trace;
132 Param
<int> split_size
;
134 Param
<bool> two_queue
;
135 Param
<bool> prefetch_miss
;
136 Param
<bool> prefetch_access
;
137 Param
<int> prefetcher_size
;
138 Param
<bool> prefetch_past_page
;
139 Param
<bool> prefetch_serial_squash
;
140 Param
<Tick
> prefetch_latency
;
141 Param
<int> prefetch_degree
;
142 Param
<string
> prefetch_policy
;
143 Param
<bool> prefetch_cache_check_push
;
144 Param
<bool> prefetch_use_cpu_id
;
145 Param
<bool> prefetch_data_accesses_only
;
146 Param
<int> hit_latency
;
148 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache
)
151 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache
)
153 INIT_PARAM(size
, "capacity in bytes"),
154 INIT_PARAM(assoc
, "associativity"),
155 INIT_PARAM(block_size
, "block size in bytes"),
156 INIT_PARAM(latency
, "hit latency in CPU cycles"),
157 INIT_PARAM(mshrs
, "number of MSHRs (max outstanding requests)"),
158 INIT_PARAM(tgts_per_mshr
, "max number of accesses per MSHR"),
159 INIT_PARAM_DFLT(write_buffers
, "number of write buffers", 8),
160 INIT_PARAM_DFLT(prioritizeRequests
, "always service demand misses first",
162 /* INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL),
163 INIT_PARAM(out_bus, "outgoing bus object"),
165 INIT_PARAM_DFLT(protocol
, "coherence protocol to use in the cache", NULL
),
166 INIT_PARAM_DFLT(trace_addr
, "address to trace", 0),
168 INIT_PARAM_DFLT(hash_delay
, "time in cycles of hash access",1),
169 #if defined(USE_CACHE_IIC)
170 INIT_PARAM_DFLT(repl
, "replacement policy",NULL
),
172 INIT_PARAM_DFLT(compressed_bus
,
173 "This cache connects to a compressed memory",
175 INIT_PARAM_DFLT(store_compressed
, "Store compressed data in the cache",
177 INIT_PARAM_DFLT(adaptive_compression
, "Use an adaptive compression scheme",
179 INIT_PARAM_DFLT(compression_latency
,
180 "Latency in cycles of compression algorithm",
182 INIT_PARAM_DFLT(subblock_size
,
183 "Size of subblock in IIC used for compression",
185 INIT_PARAM_DFLT(max_miss_count
,
186 "The number of misses to handle before calling exit",
188 /* INIT_PARAM_DFLT(hier,
189 "Hierarchy global variables",
192 INIT_PARAM_DFLT(addr_range
, "The address range in bytes",
193 vector
<Range
<Addr
> >(1,RangeIn((Addr
)0, MaxAddr
))),
194 // INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
195 INIT_PARAM_DFLT(split
, "Whether this is a partitioned cache", false),
196 INIT_PARAM_DFLT(split_size
, "the number of \"ways\" belonging to the LRU partition", 0),
197 INIT_PARAM_DFLT(lifo
, "whether you are using a LIFO repl. policy", false),
198 INIT_PARAM_DFLT(two_queue
, "whether the lifo should have two queue replacement", false),
199 INIT_PARAM_DFLT(prefetch_miss
, "wheter you are using the hardware prefetcher from Miss stream", false),
200 INIT_PARAM_DFLT(prefetch_access
, "wheter you are using the hardware prefetcher from Access stream", false),
201 INIT_PARAM_DFLT(prefetcher_size
, "Number of entries in the harware prefetch queue", 100),
202 INIT_PARAM_DFLT(prefetch_past_page
, "Allow prefetches to cross virtual page boundaries", false),
203 INIT_PARAM_DFLT(prefetch_serial_squash
, "Squash prefetches with a later time on a subsequent miss", false),
204 INIT_PARAM_DFLT(prefetch_latency
, "Latency of the prefetcher", 10),
205 INIT_PARAM_DFLT(prefetch_degree
, "Degree of the prefetch depth", 1),
206 INIT_PARAM_DFLT(prefetch_policy
, "Type of prefetcher to use", "none"),
207 INIT_PARAM_DFLT(prefetch_cache_check_push
, "Check if in cash on push or pop of prefetch queue", true),
208 INIT_PARAM_DFLT(prefetch_use_cpu_id
, "Use the CPU ID to seperate calculations of prefetches", true),
209 INIT_PARAM_DFLT(prefetch_data_accesses_only
, "Only prefetch on data not on instruction accesses", false),
210 INIT_PARAM_DFLT(hit_latency
, "Hit Latecny for a succesful access", 1)
211 END_INIT_SIM_OBJECT_PARAMS(BaseCache
)
214 #define BUILD_CACHE(t, comp, b, c) do { \
215 Prefetcher<CacheTags<t, comp>, b> *pf; \
216 if (pf_policy == "tagged") { \
217 BUILD_TAGGED_PREFETCHER(t, comp, b); \
219 else if (pf_policy == "stride") { \
220 BUILD_STRIDED_PREFETCHER(t, comp, b); \
222 else if (pf_policy == "ghb") { \
223 BUILD_GHB_PREFETCHER(t, comp, b); \
226 BUILD_NULL_PREFETCHER(t, comp, b); \
228 Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
230 /*in_bus, out_bus,*/ pf, \
231 prefetch_access, hit_latency); \
232 Cache<CacheTags<t, comp>, b, c> *retval = \
233 new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
235 /* if (in_bus == NULL) { \
236 retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
238 retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
240 retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
241 out_bus->rangeChange(); \
246 #define BUILD_CACHE_PANIC(x) do { \
247 panic("%s not compiled into M5", x); \
250 #if defined(USE_LZSS_COMPRESSION)
251 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
252 if (compressed_bus || store_compressed){ \
253 CacheTags<TAGS, LZSSCompression> *tagStore = \
254 new CacheTags<TAGS, LZSSCompression>(tags, \
255 compression_latency, \
256 true, store_compressed, \
257 adaptive_compression, \
259 BUILD_CACHE(TAGS, LZSSCompression, b, c); \
261 CacheTags<TAGS, NullCompression> *tagStore = \
262 new CacheTags<TAGS, NullCompression>(tags, \
263 compression_latency, \
264 true, store_compressed, \
265 adaptive_compression, \
267 BUILD_CACHE(TAGS, NullCompression, b, c); \
271 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
272 if (compressed_bus || store_compressed){ \
273 BUILD_CACHE_PANIC("compressed caches"); \
275 CacheTags<TAGS, NullCompression> *tagStore = \
276 new CacheTags<TAGS, NullCompression>(tags, \
277 compression_latency, \
278 true, store_compressed, \
279 adaptive_compression \
281 BUILD_CACHE(TAGS, NullCompression, b, c); \
286 #if defined(USE_CACHE_FALRU)
287 #define BUILD_FALRU_CACHE(b,c) do { \
288 FALRU *tags = new FALRU(block_size, size, latency); \
289 BUILD_COMPRESSED_CACHE(FALRU, tags, b, c); \
292 #define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
295 #if defined(USE_CACHE_LRU)
296 #define BUILD_LRU_CACHE(b, c) do { \
297 LRU *tags = new LRU(numSets, block_size, assoc, latency); \
298 BUILD_COMPRESSED_CACHE(LRU, tags, b, c); \
301 #define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
304 #if defined(USE_CACHE_SPLIT)
305 #define BUILD_SPLIT_CACHE(b, c) do { \
306 Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
307 two_queue, latency); \
308 BUILD_COMPRESSED_CACHE(Split, tags, b, c); \
311 #define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
314 #if defined(USE_CACHE_SPLIT_LIFO)
315 #define BUILD_SPLIT_LIFO_CACHE(b, c) do { \
316 SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
317 latency, two_queue, -1); \
318 BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c); \
321 #define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
324 #if defined(USE_CACHE_IIC)
325 #define BUILD_IIC_CACHE(b ,c) do { \
326 IIC *tags = new IIC(iic_params); \
327 BUILD_COMPRESSED_CACHE(IIC, tags, b, c); \
330 #define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
333 #define BUILD_CACHES(b, c) do { \
334 if (repl == NULL) { \
335 if (numSets == 1) { \
336 BUILD_FALRU_CACHE(b, c); \
338 if (split == true) { \
339 BUILD_SPLIT_CACHE(b, c); \
340 } else if (lifo == true) { \
341 BUILD_SPLIT_LIFO_CACHE(b, c); \
343 BUILD_LRU_CACHE(b, c); \
347 BUILD_IIC_CACHE(b, c); \
351 #define BUILD_COHERENCE(b) do { \
352 if (protocol == NULL) { \
353 UniCoherence *coh = new UniCoherence(); \
354 BUILD_CACHES(b, UniCoherence); \
356 SimpleCoherence *coh = new SimpleCoherence(protocol); \
357 BUILD_CACHES(b, SimpleCoherence); \
361 #if defined(USE_TAGGED)
362 #define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new \
363 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
364 !prefetch_past_page, \
365 prefetch_serial_squash, \
366 prefetch_cache_check_push, \
367 prefetch_data_accesses_only, \
371 #define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
374 #if defined(USE_STRIDED)
375 #define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new \
376 StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
377 !prefetch_past_page, \
378 prefetch_serial_squash, \
379 prefetch_cache_check_push, \
380 prefetch_data_accesses_only, \
385 #define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
389 #define BUILD_GHB_PREFETCHER(t, comp, b) pf = new \
390 GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
391 !prefetch_past_page, \
392 prefetch_serial_squash, \
393 prefetch_cache_check_push, \
394 prefetch_data_accesses_only, \
399 #define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
402 #if defined(USE_TAGGED)
403 #define BUILD_NULL_PREFETCHER(t, comp, b) pf = new \
404 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
405 !prefetch_past_page, \
406 prefetch_serial_squash, \
407 prefetch_cache_check_push, \
408 prefetch_data_accesses_only, \
412 #define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
415 CREATE_SIM_OBJECT(BaseCache
)
417 string name
= getInstanceName();
418 int numSets
= size
/ (assoc
* block_size
);
419 string pf_policy
= prefetch_policy
;
420 if (subblock_size
== 0) {
421 subblock_size
= block_size
;
424 // Build BaseCache param object
425 BaseCache::Params
base_params(addr_range
, latency
,
426 block_size
, max_miss_count
);
428 //Warnings about prefetcher policy
429 if (pf_policy
== "none" && (prefetch_miss
|| prefetch_access
)) {
430 panic("With no prefetcher, you shouldn't prefetch from"
431 " either miss or access stream\n");
433 if ((pf_policy
== "tagged" || pf_policy
== "stride" ||
434 pf_policy
== "ghb") && !(prefetch_miss
|| prefetch_access
)) {
435 warn("With this prefetcher you should chose a prefetch"
436 " stream (miss or access)\nNo Prefetching will occur\n");
438 if ((pf_policy
== "tagged" || pf_policy
== "stride" ||
439 pf_policy
== "ghb") && prefetch_miss
&& prefetch_access
) {
440 panic("Can't do prefetches from both miss and access"
443 if (pf_policy
!= "tagged" && pf_policy
!= "stride" &&
444 pf_policy
!= "ghb" && pf_policy
!= "none") {
445 panic("Unrecognized form of a prefetcher: %s, try using"
446 "['none','stride','tagged','ghb']\n", pf_policy
);
449 #if defined(USE_CACHE_IIC)
451 IIC::Params iic_params
;
452 iic_params
.size
= size
;
453 iic_params
.numSets
= numSets
;
454 iic_params
.blkSize
= block_size
;
455 iic_params
.assoc
= assoc
;
456 iic_params
.hashDelay
= hash_delay
;
457 iic_params
.hitLatency
= latency
;
458 iic_params
.rp
= repl
;
459 iic_params
.subblockSize
= subblock_size
;
461 const void *repl
= NULL
;
464 if (mshrs
== 1 /*|| out_bus->doEvents() == false*/) {
465 BlockingBuffer
*mq
= new BlockingBuffer(true);
466 BUILD_COHERENCE(BlockingBuffer
);
468 MissQueue
*mq
= new MissQueue(mshrs
, tgts_per_mshr
, write_buffers
,
469 true, prefetch_miss
);
470 BUILD_COHERENCE(MissQueue
);
475 REGISTER_SIM_OBJECT("BaseCache", BaseCache
)
478 #endif //DOXYGEN_SHOULD_SKIP_THIS