src/mem/cache/cache_builder.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Nathan Binkert
  30  */
  31
  32 /**
  33  * @file
  34  * Simobject instatiation of caches.
  35  */
  36 #include <vector>
  37
  38 // Must be included first to determine which caches we want
  39 #include "mem/config/cache.hh"
  40 #include "mem/config/compression.hh"
  41 #include "mem/config/prefetch.hh"
  42
  43 #include "mem/cache/base_cache.hh"
  44 #include "mem/cache/cache.hh"
  45 #include "mem/bus/bus.hh"
  46 #include "mem/cache/coherence/coherence_protocol.hh"
  47 #include "sim/builder.hh"
  48
  49 // Tag Templates
  50 #if defined(USE_CACHE_LRU)
  51 #include "mem/cache/tags/lru.hh"
  52 #endif
  53
  54 #if defined(USE_CACHE_FALRU)
  55 #include "mem/cache/tags/fa_lru.hh"
  56 #endif
  57
  58 #if defined(USE_CACHE_IIC)
  59 #include "mem/cache/tags/iic.hh"
  60 #endif
  61
  62 #if defined(USE_CACHE_SPLIT)
  63 #include "mem/cache/tags/split.hh"
  64 #endif
  65
  66 #if defined(USE_CACHE_SPLIT_LIFO)
  67 #include "mem/cache/tags/split_lifo.hh"
  68 #endif
  69
  70 // Compression Templates
  71 #include "base/compression/null_compression.hh"
  72 #if defined(USE_LZSS_COMPRESSION)
  73 #include "base/compression/lzss_compression.hh"
  74 #endif
  75
  76 // CacheTags Templates
  77 #include "mem/cache/tags/cache_tags.hh"
  78
  79 // MissQueue Templates
  80 #include "mem/cache/miss/miss_queue.hh"
  81 #include "mem/cache/miss/blocking_buffer.hh"
  82
  83 // Coherence Templates
  84 #include "mem/cache/coherence/uni_coherence.hh"
  85 #include "mem/cache/coherence/simple_coherence.hh"
  86
  87 // Bus Interfaces
  88 #include "mem/bus/slave_interface.hh"
  89 #include "mem/bus/master_interface.hh"
  90 #include "mem/memory_interface.hh"
  91
  92 #include "mem/trace/mem_trace_writer.hh"
  93
  94 //Prefetcher Headers
  95 #if defined(USE_GHB)
  96 #include "mem/cache/prefetch/ghb_prefetcher.hh"
  97 #endif
  98 #if defined(USE_TAGGED)
  99 #include "mem/cache/prefetch/tagged_prefetcher.hh"
 100 #endif
 101 #if defined(USE_STRIDED)
 102 #include "mem/cache/prefetch/stride_prefetcher.hh"
 103 #endif
 104
 105
 106 using namespace std;
 107 using namespace TheISA;
 108
 109 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 110
 111 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 112
 113     Param<int> size;
 114     Param<int> assoc;
 115     Param<int> block_size;
 116     Param<int> latency;
 117     Param<int> mshrs;
 118     Param<int> tgts_per_mshr;
 119     Param<int> write_buffers;
 120     Param<bool> prioritizeRequests;
 121     SimObjectParam<Bus *> in_bus;
 122     SimObjectParam<Bus *> out_bus;
 123     Param<bool> do_copy;
 124     SimObjectParam<CoherenceProtocol *> protocol;
 125     Param<Addr> trace_addr;
 126     Param<int> hash_delay;
 127 #if defined(USE_CACHE_IIC)
 128     SimObjectParam<Repl *> repl;
 129 #endif
 130     Param<bool> compressed_bus;
 131     Param<bool> store_compressed;
 132     Param<bool> adaptive_compression;
 133     Param<int> compression_latency;
 134     Param<int> subblock_size;
 135     Param<Counter> max_miss_count;
 136     SimObjectParam<HierParams *> hier;
 137     VectorParam<Range<Addr> > addr_range;
 138     SimObjectParam<MemTraceWriter *> mem_trace;
 139     Param<bool> split;
 140     Param<int> split_size;
 141     Param<bool> lifo;
 142     Param<bool> two_queue;
 143     Param<bool> prefetch_miss;
 144     Param<bool> prefetch_access;
 145     Param<int> prefetcher_size;
 146     Param<bool> prefetch_past_page;
 147     Param<bool> prefetch_serial_squash;
 148     Param<Tick> prefetch_latency;
 149     Param<int> prefetch_degree;
 150     Param<string> prefetch_policy;
 151     Param<bool> prefetch_cache_check_push;
 152     Param<bool> prefetch_use_cpu_id;
 153     Param<bool> prefetch_data_accesses_only;
 154
 155 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 156
 157
 158 BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
 159
 160     INIT_PARAM(size, "capacity in bytes"),
 161     INIT_PARAM(assoc, "associativity"),
 162     INIT_PARAM(block_size, "block size in bytes"),
 163     INIT_PARAM(latency, "hit latency in CPU cycles"),
 164     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
 165     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
 166     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
 167     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
 168                     false),
 169     INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL),
 170     INIT_PARAM(out_bus, "outgoing bus object"),
 171     INIT_PARAM_DFLT(do_copy, "perform fast copies in the cache", false),
 172     INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
 173     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 174
 175     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
 176 #if defined(USE_CACHE_IIC)
 177     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
 178 #endif
 179     INIT_PARAM_DFLT(compressed_bus,
 180                     "This cache connects to a compressed memory",
 181                     false),
 182     INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
 183                     false),
 184     INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
 185                     false),
 186     INIT_PARAM_DFLT(compression_latency,
 187                     "Latency in cycles of compression algorithm",
 188                     0),
 189     INIT_PARAM_DFLT(subblock_size,
 190                     "Size of subblock in IIC used for compression",
 191                     0),
 192     INIT_PARAM_DFLT(max_miss_count,
 193                     "The number of misses to handle before calling exit",
 194                     0),
 195     INIT_PARAM_DFLT(hier,
 196                     "Hierarchy global variables",
 197                     &defaultHierParams),
 198     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
 199                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
 200     INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
 201     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
 202     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
 203     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
 204     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
 205     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
 206     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
 207     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
 208     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
 209     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
 210     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
 211     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
 212     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
 213     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
 214     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
 215     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
 216 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 217
 218
 219 #define BUILD_CACHE(t, comp, b, c) do {                                 \
 220         Prefetcher<CacheTags<t, comp>, b> *pf; \
 221         if (pf_policy == "tagged") {      \
 222              BUILD_TAGGED_PREFETCHER(t, comp, b); \
 223         }            \
 224         else if (pf_policy == "stride") {       \
 225              BUILD_STRIDED_PREFETCHER(t, comp, b); \
 226         } \
 227         else if (pf_policy == "ghb") {       \
 228              BUILD_GHB_PREFETCHER(t, comp, b); \
 229         } \
 230         else { \
 231              BUILD_NULL_PREFETCHER(t, comp, b); \
 232         } \
 233         Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
 234                                                        do_copy, base_params, \
 235                                                        in_bus, out_bus, pf,  \
 236                                                        prefetch_access); \
 237         Cache<CacheTags<t, comp>, b, c> *retval =                       \
 238             new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), hier, \
 239                                                 params);                \
 240         if (in_bus == NULL) {                                           \
 241             retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
 242         } else {                                                        \
 243             retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
 244         }                                                               \
 245         retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
 246         out_bus->rangeChange();                                         \
 247         return retval;                                                  \
 248     } while (0)
 249
 250 #define BUILD_CACHE_PANIC(x) do {                       \
 251         panic("%s not compiled into M5", x);            \
 252     } while (0)
 253
 254 #if defined(USE_LZSS_COMPRESSION)
 255 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
 256         if (compressed_bus || store_compressed){                        \
 257             CacheTags<TAGS, LZSSCompression> *tagStore =                \
 258                 new CacheTags<TAGS, LZSSCompression>(tags,              \
 259                                                      compression_latency, \
 260                                                      true, store_compressed, \
 261                                                      adaptive_compression,   \
 262                                                      prefetch_miss); \
 263             BUILD_CACHE(TAGS, LZSSCompression, b, c);                   \
 264         } else {                                                        \
 265             CacheTags<TAGS, NullCompression> *tagStore =                \
 266                 new CacheTags<TAGS, NullCompression>(tags,              \
 267                                                      compression_latency, \
 268                                                      true, store_compressed, \
 269                                                      adaptive_compression,   \
 270                                                      prefetch_miss); \
 271             BUILD_CACHE(TAGS, NullCompression, b, c);                   \
 272         }                                                               \
 273     } while (0)
 274 #else
 275 #define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
 276         if (compressed_bus || store_compressed){                        \
 277             BUILD_CACHE_PANIC("compressed caches");                     \
 278         } else {                                                        \
 279             CacheTags<TAGS, NullCompression> *tagStore =                \
 280                 new CacheTags<TAGS, NullCompression>(tags,              \
 281                                                       compression_latency, \
 282                                                       true, store_compressed, \
 283                                                       adaptive_compression    \
 284                                                       prefetch_miss); \
 285             BUILD_CACHE(TAGS, NullCompression, b, c);                   \
 286         }                                                               \
 287     } while (0)
 288 #endif
 289
 290 #if defined(USE_CACHE_FALRU)
 291 #define BUILD_FALRU_CACHE(b,c) do {                         \
 292         FALRU *tags = new FALRU(block_size, size, latency); \
 293         BUILD_COMPRESSED_CACHE(FALRU, tags, b, c);              \
 294     } while (0)
 295 #else
 296 #define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
 297 #endif
 298
 299 #if defined(USE_CACHE_LRU)
 300 #define BUILD_LRU_CACHE(b, c) do {                              \
 301         LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
 302         BUILD_COMPRESSED_CACHE(LRU, tags, b, c);                        \
 303     } while (0)
 304 #else
 305 #define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
 306 #endif
 307
 308 #if defined(USE_CACHE_SPLIT)
 309 #define BUILD_SPLIT_CACHE(b, c) do {                                    \
 310         Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
 311                                 two_queue, latency);            \
 312         BUILD_COMPRESSED_CACHE(Split, tags, b, c);                      \
 313     } while (0)
 314 #else
 315 #define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
 316 #endif
 317
 318 #if defined(USE_CACHE_SPLIT_LIFO)
 319 #define BUILD_SPLIT_LIFO_CACHE(b, c) do {                               \
 320         SplitLIFO *tags = new SplitLIFO(block_size, size, assoc,        \
 321                                         latency, two_queue, -1);        \
 322         BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c);                  \
 323     } while (0)
 324 #else
 325 #define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
 326 #endif
 327
 328 #if defined(USE_CACHE_IIC)
 329 #define BUILD_IIC_CACHE(b ,c) do {                      \
 330         IIC *tags = new IIC(iic_params);                \
 331         BUILD_COMPRESSED_CACHE(IIC, tags, b, c);        \
 332     } while (0)
 333 #else
 334 #define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
 335 #endif
 336
 337 #define BUILD_CACHES(b, c) do {                         \
 338         if (repl == NULL) {                             \
 339             if (numSets == 1) {                         \
 340                 BUILD_FALRU_CACHE(b, c);                \
 341             } else {                                    \
 342                 if (split == true) {                    \
 343                     BUILD_SPLIT_CACHE(b, c);            \
 344                 } else if (lifo == true) {              \
 345                     BUILD_SPLIT_LIFO_CACHE(b, c);       \
 346                 } else {                                \
 347                     BUILD_LRU_CACHE(b, c);              \
 348                 }                                       \
 349             }                                           \
 350         } else {                                        \
 351             BUILD_IIC_CACHE(b, c);                      \
 352         }                                               \
 353     } while (0)
 354
 355 #define BUILD_COHERENCE(b) do {                                         \
 356         if (protocol == NULL) {                                         \
 357             UniCoherence *coh = new UniCoherence();                     \
 358             BUILD_CACHES(b, UniCoherence);                              \
 359         } else {                                                        \
 360             SimpleCoherence *coh = new SimpleCoherence(protocol);       \
 361             BUILD_CACHES(b, SimpleCoherence);                           \
 362         }                                                               \
 363     } while (0)
 364
 365 #if defined(USE_TAGGED)
 366 #define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new   \
 367                 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 368                                                         !prefetch_past_page, \
 369                                                         prefetch_serial_squash, \
 370                                                         prefetch_cache_check_push, \
 371                                                         prefetch_data_accesses_only, \
 372                                                         prefetch_latency, \
 373                                                         prefetch_degree)
 374 #else
 375 #define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
 376 #endif
 377
 378 #if defined(USE_STRIDED)
 379 #define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new  \
 380                 StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 381                                                         !prefetch_past_page, \
 382                                                         prefetch_serial_squash, \
 383                                                         prefetch_cache_check_push, \
 384                                                         prefetch_data_accesses_only, \
 385                                                         prefetch_latency, \
 386                                                         prefetch_degree, \
 387                                                         prefetch_use_cpu_id)
 388 #else
 389 #define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
 390 #endif
 391
 392 #if defined(USE_GHB)
 393 #define BUILD_GHB_PREFETCHER(t, comp, b) pf = new  \
 394                 GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 395                                                      !prefetch_past_page, \
 396                                                      prefetch_serial_squash, \
 397                                                      prefetch_cache_check_push, \
 398                                                         prefetch_data_accesses_only, \
 399                                                      prefetch_latency, \
 400                                                      prefetch_degree, \
 401                                                      prefetch_use_cpu_id)
 402 #else
 403 #define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
 404 #endif
 405
 406 #if defined(USE_TAGGED)
 407 #define BUILD_NULL_PREFETCHER(t, comp, b) pf = new  \
 408                 TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
 409                                                         !prefetch_past_page, \
 410                                                         prefetch_serial_squash, \
 411                                                         prefetch_cache_check_push, \
 412                                                         prefetch_data_accesses_only, \
 413                                                         prefetch_latency, \
 414                                                         prefetch_degree)
 415 #else
 416 #define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 417 #endif
 418
 419 CREATE_SIM_OBJECT(BaseCache)
 420 {
 421     string name = getInstanceName();
 422     int numSets = size / (assoc * block_size);
 423     string pf_policy = prefetch_policy;
 424     if (subblock_size == 0) {
 425         subblock_size = block_size;
 426     }
 427
 428     // Build BaseCache param object
 429     BaseCache::Params base_params(addr_range, latency,
 430                                   block_size, max_miss_count);
 431
 432     //Warnings about prefetcher policy
 433     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
 434         panic("With no prefetcher, you shouldn't prefetch from"
 435               " either miss or access stream\n");
 436     }
 437     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 438          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
 439         warn("With this prefetcher you should chose a prefetch"
 440              " stream (miss or access)\nNo Prefetching will occur\n");
 441     }
 442     if ((pf_policy == "tagged" || pf_policy == "stride" ||
 443          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
 444         panic("Can't do prefetches from both miss and access"
 445               " stream\n");
 446     }
 447     if (pf_policy != "tagged" && pf_policy != "stride" &&
 448         pf_policy != "ghb"    && pf_policy != "none") {
 449         panic("Unrecognized form of a prefetcher: %s, try using"
 450               "['none','stride','tagged','ghb']\n", pf_policy);
 451     }
 452
 453 #if defined(USE_CACHE_IIC)
 454     // Build IIC params
 455     IIC::Params iic_params;
 456     iic_params.size = size;
 457     iic_params.numSets = numSets;
 458     iic_params.blkSize = block_size;
 459     iic_params.assoc = assoc;
 460     iic_params.hashDelay = hash_delay;
 461     iic_params.hitLatency = latency;
 462     iic_params.rp = repl;
 463     iic_params.subblockSize = subblock_size;
 464 #else
 465     const void *repl = NULL;
 466 #endif
 467
 468     if (mshrs == 1 || out_bus->doEvents() == false) {
 469         BlockingBuffer *mq = new BlockingBuffer(true);
 470         BUILD_COHERENCE(BlockingBuffer);
 471     } else {
 472         MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
 473                                       true, prefetch_miss);
 474         BUILD_COHERENCE(MissQueue);
 475     }
 476     return NULL;
 477 }
 478
 479 REGISTER_SIM_OBJECT("BaseCache", BaseCache)
 480
 481
 482 #endif //DOXYGEN_SHOULD_SKIP_THIS