2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_events.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
67 if (pkt->isResponse())
75 template<class TagStore, class Buffering, class Coherence>
77 Cache<TagStore,Buffering,Coherence>::
78 doAtomicAccess(Packet *pkt, bool isCpuSide)
83 //TEMP ALWAYS SUCCES FOR NOW
84 pkt->result = Packet::Success;
88 if (pkt->isResponse())
91 snoopProbe(pkt, true);
93 //Fix this timing info
97 template<class TagStore, class Buffering, class Coherence>
99 Cache<TagStore,Buffering,Coherence>::
100 doFunctionalAccess(Packet *pkt, bool isCpuSide)
104 //TEMP USE CPU?THREAD 0 0
105 pkt->req->setThreadContext(0,0);
107 //TEMP ALWAYS SUCCESFUL FOR NOW
108 pkt->result = Packet::Success;
112 if (pkt->isResponse())
115 snoopProbe(pkt, true);
119 template<class TagStore, class Buffering, class Coherence>
121 Cache<TagStore,Buffering,Coherence>::
122 recvStatusChange(Port::Status status, bool isCpuSide)
128 template<class TagStore, class Buffering, class Coherence>
129 Cache<TagStore,Buffering,Coherence>::
130 Cache(const std::string &_name,
131 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
132 : BaseCache(_name, params.baseParams),
133 prefetchAccess(params.prefetchAccess),
134 tags(params.tags), missQueue(params.missQueue),
135 coherence(params.coherence), prefetcher(params.prefetcher),
136 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
139 // if (params.in == NULL) {
140 topLevelCache = true;
142 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
143 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
144 tags->setPrefetcher(prefetcher);
145 missQueue->setCache(this);
146 missQueue->setPrefetcher(prefetcher);
147 coherence->setCache(this);
148 prefetcher->setCache(this);
149 prefetcher->setTags(tags);
150 prefetcher->setBuffer(missQueue);
152 invalidatePkt = new Packet;
153 invalidatePkt->cmd = Packet::InvalidateReq;
157 template<class TagStore, class Buffering, class Coherence>
159 Cache<TagStore,Buffering,Coherence>::regStats()
161 BaseCache::regStats();
162 tags->regStats(name());
163 missQueue->regStats(name());
164 coherence->regStats(name());
165 prefetcher->regStats(name());
168 template<class TagStore, class Buffering, class Coherence>
170 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
172 //@todo Add back in MemDebug Calls
173 // MemDebug::cacheAccess(pkt);
175 PacketList writebacks;
177 int lat = hitLatency;
178 if (prefetchAccess) {
179 //We are determining prefetches on access stream, call prefetcher
180 prefetcher->handleMiss(pkt, curTick);
182 if (!pkt->req->isUncacheable()) {
183 if (pkt->isInvalidate() && !pkt->isRead()
184 && !pkt->isWrite()) {
185 //Upgrade or Invalidate
186 //Look into what happens if two slave caches on bus
187 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
188 pkt->getAddr() & (((ULL(1))<<48)-1),
189 pkt->getAddr() & ~((Addr)blkSize - 1));
191 //@todo Should this return latency have the hit latency in it?
192 // respond(pkt,curTick+lat);
193 pkt->flags |= SATISFIED;
194 // return MA_HIT; //@todo, return values
197 blk = tags->handleAccess(pkt, lat, writebacks);
199 size = pkt->getSize();
201 // If this is a block size write/hint (WH64) allocate the block here
202 // if the coherence protocol allows it.
203 /** @todo make the fast write alloc (wh64) work with coherence. */
204 /** @todo Do we want to do fast writes for writebacks as well? */
205 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
206 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
207 // not outstanding misses, can do this
208 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
209 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
210 if (outstanding_miss) {
211 warn("WriteInv doing a fastallocate"
212 "with an outstanding miss to the same address\n");
214 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
219 while (!writebacks.empty()) {
220 missQueue->doWriteback(writebacks.front());
221 writebacks.pop_front();
223 DPRINTF(Cache, "%s %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
224 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
225 pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
228 hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
229 // clear dirty bit if write through
230 if (pkt->needsResponse())
231 respond(pkt, curTick+lat);
237 if (!pkt->req->isUncacheable()) {
238 misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
239 /** @todo Move miss count code into BaseCache */
243 new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
246 missQueue->handleMiss(pkt, size, curTick + hitLatency);
247 // return MA_CACHE_MISS;
252 template<class TagStore, class Buffering, class Coherence>
254 Cache<TagStore,Buffering,Coherence>::getPacket()
256 Packet * pkt = missQueue->getPacket();
258 if (!pkt->req->isUncacheable()) {
259 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
260 BlkType *blk = tags->findBlock(pkt);
261 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
262 (blk)? blk->status : 0);
263 missQueue->setBusCmd(pkt, cmd);
267 assert(!doMasterRequest() || missQueue->havePending());
268 assert(!pkt || pkt->time <= curTick);
272 template<class TagStore, class Buffering, class Coherence>
274 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
277 missQueue->markInService(pkt);
278 //Temp Hack for UPGRADES
279 if (pkt->cmd == Packet::UpgradeReq) {
282 } else if (pkt && !pkt->req->isUncacheable()) {
283 missQueue->restoreOrigCmd(pkt);
287 template<class TagStore, class Buffering, class Coherence>
289 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
292 if (pkt->senderState) {
293 // MemDebug::cacheResponse(pkt);
294 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
295 pkt->getAddr() & (((ULL(1))<<48)-1));
297 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
298 blk = tags->findBlock(pkt);
299 CacheBlk::State old_state = (blk) ? blk->status : 0;
300 PacketList writebacks;
301 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
302 coherence->getNewState(pkt,old_state),
304 while (!writebacks.empty()) {
305 missQueue->doWriteback(writebacks.front());
308 missQueue->handleResponse(pkt, curTick + hitLatency);
312 template<class TagStore, class Buffering, class Coherence>
314 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
316 // Need to temporarily move this blk into MSHRs
317 MSHR *mshr = missQueue->allocateTargetList(addr);
320 // Read the data into the mshr
321 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
322 assert(dummy.empty());
323 assert(mshr->pkt->flags & SATISFIED);
324 // can overload order since it isn't used on non pending blocks
325 mshr->order = blk->status;
326 // temporarily remove the block from the cache.
327 tags->invalidateBlk(addr);
330 template<class TagStore, class Buffering, class Coherence>
332 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
334 // Need to temporarily move this blk into MSHRs
335 assert(mshr->pkt->cmd == Packet::ReadReq);
338 // Read the data into the mshr
339 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
340 assert(dummy.empty());
341 assert(mshr->pkt->flags & SATISFIED);
342 // can overload order since it isn't used on non pending blocks
343 mshr->order = blk->status;
344 // temporarily remove the block from the cache.
345 tags->invalidateBlk(mshr->pkt->getAddr());
349 template<class TagStore, class Buffering, class Coherence>
351 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
353 return coherence->getPacket();
357 template<class TagStore, class Buffering, class Coherence>
359 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
362 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
363 BlkType *blk = tags->findBlock(pkt);
364 MSHR *mshr = missQueue->findMSHR(blk_addr);
365 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
366 //If we find an mshr, and it is in service, we need to NACK or invalidate
368 if (mshr->inService) {
369 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
370 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
371 //If the outstanding request was an invalidate (upgrade,readex,..)
372 //Then we need to ACK the request until we get the data
373 //Also NACK if the outstanding request is not a cachefill (writeback)
374 pkt->flags |= NACKED_LINE;
378 //The supplier will be someone else, because we are waiting for
379 //the data. This should cause this cache to be forced to go to
380 //the shared state, not the exclusive even though the shared line
381 //won't be asserted. But for now we will just invlidate ourselves
382 //and allow the other cache to go into the exclusive state.
383 //@todo Make it so a read to a pending read doesn't invalidate.
384 //@todo Make it so that a read to a pending read can't be exclusive now.
386 //Set the address so find match works
387 invalidatePkt->addrOverride(pkt->getAddr());
389 //Append the invalidate on
390 missQueue->addTarget(mshr,invalidatePkt);
391 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
396 //We also need to check the writeback buffers and handle those
397 std::vector<MSHR *> writebacks;
398 if (missQueue->findWrites(blk_addr, writebacks)) {
399 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
401 //Look through writebacks for any non-uncachable writes, use that
402 for (int i=0; i<writebacks.size(); i++) {
403 mshr = writebacks[i];
405 if (!mshr->pkt->req->isUncacheable()) {
407 //Only Upgrades don't get here
409 pkt->flags |= SATISFIED;
411 //If we are in an exclusive protocol, make it ask again
412 //to get write permissions (upgrade), signal shared
413 pkt->flags |= SHARED_LINE;
415 assert(pkt->isRead());
416 Addr offset = pkt->getAddr() & ~(blkSize - 1);
417 assert(offset < blkSize);
418 assert(pkt->getSize() <= blkSize);
419 assert(offset + pkt->getSize() <=blkSize);
420 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
425 if (pkt->isInvalidate()) {
426 //This must be an upgrade or other cache will take ownership
427 missQueue->markInService(mshr->pkt);
434 CacheBlk::State new_state;
435 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
437 tags->handleSnoop(blk, new_state, pkt);
441 tags->handleSnoop(blk, new_state);
444 template<class TagStore, class Buffering, class Coherence>
446 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
448 //Need to handle the response, if NACKED
449 if (pkt->flags & NACKED_LINE) {
450 //Need to mark it as not in service, and retry for bus
451 assert(0); //Yeah, we saw a NACK come through
453 //For now this should never get called, we return false when we see a NACK
454 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
455 //For now it retrys in just 2 cycles, need to figure out how to change that
456 //Eventually we will want to also have success come in as a parameter
457 //Need to make sure that we handle the functionality that happens on successufl
458 //return of the sendAddr function
462 template<class TagStore, class Buffering, class Coherence>
464 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
466 tags->invalidateBlk(addr);
471 * @todo Fix to not assume write allocate
473 template<class TagStore, class Buffering, class Coherence>
475 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
477 // MemDebug::cacheProbe(pkt);
478 if (!pkt->req->isUncacheable()) {
479 if (pkt->isInvalidate() && !pkt->isRead()
480 && !pkt->isWrite()) {
481 //Upgrade or Invalidate, satisfy it, don't forward
482 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
483 pkt->getAddr() & (((ULL(1))<<48)-1),
484 pkt->getAddr() & ~((Addr)blkSize - 1));
485 pkt->flags |= SATISFIED;
490 PacketList writebacks;
492 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
495 // Need to check for outstanding misses and writes
496 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
498 // There can only be one matching outstanding miss.
499 MSHR* mshr = missQueue->findMSHR(blk_addr);
501 // There can be many matching outstanding writes.
502 std::vector<MSHR*> writes;
503 missQueue->findWrites(blk_addr, writes);
506 memSidePort->sendFunctional(pkt);
507 // Check for data in MSHR and writebuffer.
509 warn("Found outstanding miss on an non-update probe");
510 MSHR::TargetList *targets = mshr->getTargetList();
511 MSHR::TargetList::iterator i = targets->begin();
512 MSHR::TargetList::iterator end = targets->end();
513 for (; i != end; ++i) {
514 Packet * target = *i;
515 // If the target contains data, and it overlaps the
516 // probed request, need to update data
517 if (target->isWrite() && target->intersect(pkt)) {
521 if (target->getAddr() < pkt->getAddr()) {
522 int offset = pkt->getAddr() - target->getAddr();
523 pkt_data = pkt->getPtr<uint8_t>();
524 write_data = target->getPtr<uint8_t>() + offset;
525 data_size = target->getSize() - offset;
526 assert(data_size > 0);
527 if (data_size > pkt->getSize())
528 data_size = pkt->getSize();
530 int offset = target->getAddr() - pkt->getAddr();
531 pkt_data = pkt->getPtr<uint8_t>() + offset;
532 write_data = target->getPtr<uint8_t>();
533 data_size = pkt->getSize() - offset;
534 assert(data_size > pkt->getSize());
535 if (data_size > target->getSize())
536 data_size = target->getSize();
539 if (pkt->isWrite()) {
540 memcpy(pkt_data, write_data, data_size);
542 memcpy(write_data, pkt_data, data_size);
547 for (int i = 0; i < writes.size(); ++i) {
548 Packet * write = writes[i]->pkt;
549 if (write->intersect(pkt)) {
550 warn("Found outstanding write on an non-update probe");
554 if (write->getAddr() < pkt->getAddr()) {
555 int offset = pkt->getAddr() - write->getAddr();
556 pkt_data = pkt->getPtr<uint8_t>();
557 write_data = write->getPtr<uint8_t>() + offset;
558 data_size = write->getSize() - offset;
559 assert(data_size > 0);
560 if (data_size > pkt->getSize())
561 data_size = pkt->getSize();
563 int offset = write->getAddr() - pkt->getAddr();
564 pkt_data = pkt->getPtr<uint8_t>() + offset;
565 write_data = write->getPtr<uint8_t>();
566 data_size = pkt->getSize() - offset;
567 assert(data_size > pkt->getSize());
568 if (data_size > write->getSize())
569 data_size = write->getSize();
572 if (pkt->isWrite()) {
573 memcpy(pkt_data, write_data, data_size);
575 memcpy(write_data, pkt_data, data_size);
582 // update the cache state and statistics
583 if (mshr || !writes.empty()){
584 // Can't handle it, return pktuest unsatisfied.
587 if (!pkt->req->isUncacheable()) {
588 // Fetch the cache block to fill
589 BlkType *blk = tags->findBlock(pkt);
590 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
591 (blk)? blk->status : 0);
593 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
597 busPkt->time = curTick;
599 lat = memSidePort->sendAtomic(busPkt);
601 /* if (!(busPkt->flags & SATISFIED)) {
602 // blocked at a higher level, just return
606 */ misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
608 CacheBlk::State old_state = (blk) ? blk->status : 0;
609 tags->handleFill(blk, busPkt,
610 coherence->getNewState(busPkt, old_state),
612 // Handle writebacks if needed
613 while (!writebacks.empty()){
614 memSidePort->sendAtomic(writebacks.front());
615 writebacks.pop_front();
617 return lat + hitLatency;
619 return memSidePort->sendAtomic(pkt);
623 // There was a cache hit.
624 // Handle writebacks if needed
625 while (!writebacks.empty()){
626 memSidePort->sendAtomic(writebacks.front());
627 writebacks.pop_front();
631 hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
632 } else if (pkt->isWrite()) {
633 // Still need to change data in all locations.
634 return memSidePort->sendAtomic(pkt);
636 return curTick + lat;
638 fatal("Probe not handled.\n");
642 template<class TagStore, class Buffering, class Coherence>
644 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
646 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
647 BlkType *blk = tags->findBlock(pkt);
648 MSHR *mshr = missQueue->findMSHR(blk_addr);
649 CacheBlk::State new_state = 0;
650 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
652 tags->handleSnoop(blk, new_state, pkt);
655 tags->handleSnoop(blk, new_state);