2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
64 pkt->req->setScResult(1);
66 if (!(pkt->flags & SATISFIED)) {
72 if (pkt->isResponse())
75 //Check if we are in phase1
80 //Check if we should do the snoop
81 if (pkt->flags && SNOOP_COMMIT)
90 template<class TagStore, class Buffering, class Coherence>
92 Cache<TagStore,Buffering,Coherence>::
93 doAtomicAccess(Packet *pkt, bool isCpuSide)
97 //Temporary solution to LL/SC
98 if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
99 pkt->req->setScResult(1);
102 probe(pkt, true, NULL);
103 //TEMP ALWAYS SUCCES FOR NOW
104 pkt->result = Packet::Success;
108 if (pkt->isResponse())
113 //Fix this timing info
117 template<class TagStore, class Buffering, class Coherence>
119 Cache<TagStore,Buffering,Coherence>::
120 doFunctionalAccess(Packet *pkt, bool isCpuSide)
124 //TEMP USE CPU?THREAD 0 0
125 pkt->req->setThreadContext(0,0);
127 //Temporary solution to LL/SC
128 if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
129 assert("Can't handle LL/SC on functional path\n");
132 probe(pkt, false, memSidePort);
133 //TEMP ALWAYS SUCCESFUL FOR NOW
134 pkt->result = Packet::Success;
138 probe(pkt, false, cpuSidePort);
142 template<class TagStore, class Buffering, class Coherence>
144 Cache<TagStore,Buffering,Coherence>::
145 recvStatusChange(Port::Status status, bool isCpuSide)
151 template<class TagStore, class Buffering, class Coherence>
152 Cache<TagStore,Buffering,Coherence>::
153 Cache(const std::string &_name,
154 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
155 : BaseCache(_name, params.baseParams),
156 prefetchAccess(params.prefetchAccess),
157 tags(params.tags), missQueue(params.missQueue),
158 coherence(params.coherence), prefetcher(params.prefetcher),
159 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
162 // if (params.in == NULL) {
163 topLevelCache = true;
165 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
166 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
167 tags->setPrefetcher(prefetcher);
168 missQueue->setCache(this);
169 missQueue->setPrefetcher(prefetcher);
170 coherence->setCache(this);
171 prefetcher->setCache(this);
172 prefetcher->setTags(tags);
173 prefetcher->setBuffer(missQueue);
175 invalidatePkt = new Packet;
176 invalidatePkt->cmd = Packet::InvalidateReq;
180 template<class TagStore, class Buffering, class Coherence>
182 Cache<TagStore,Buffering,Coherence>::regStats()
184 BaseCache::regStats();
185 tags->regStats(name());
186 missQueue->regStats(name());
187 coherence->regStats(name());
188 prefetcher->regStats(name());
191 template<class TagStore, class Buffering, class Coherence>
193 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
195 //@todo Add back in MemDebug Calls
196 // MemDebug::cacheAccess(pkt);
198 PacketList writebacks;
200 int lat = hitLatency;
201 if (prefetchAccess) {
202 //We are determining prefetches on access stream, call prefetcher
203 prefetcher->handleMiss(pkt, curTick);
205 if (!pkt->req->isUncacheable()) {
206 if (pkt->isInvalidate() && !pkt->isRead()
207 && !pkt->isWrite()) {
208 //Upgrade or Invalidate
209 //Look into what happens if two slave caches on bus
210 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
211 pkt->getAddr() & (((ULL(1))<<48)-1),
212 pkt->getAddr() & ~((Addr)blkSize - 1));
214 //@todo Should this return latency have the hit latency in it?
215 // respond(pkt,curTick+lat);
216 pkt->flags |= SATISFIED;
217 // return MA_HIT; //@todo, return values
220 blk = tags->handleAccess(pkt, lat, writebacks);
222 size = pkt->getSize();
224 // If this is a block size write/hint (WH64) allocate the block here
225 // if the coherence protocol allows it.
226 /** @todo make the fast write alloc (wh64) work with coherence. */
227 /** @todo Do we want to do fast writes for writebacks as well? */
228 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
229 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
230 // not outstanding misses, can do this
231 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
232 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
233 if (outstanding_miss) {
234 warn("WriteInv doing a fastallocate"
235 "with an outstanding miss to the same address\n");
237 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
242 while (!writebacks.empty()) {
243 missQueue->doWriteback(writebacks.front());
244 writebacks.pop_front();
246 DPRINTF(Cache, "%s %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
247 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
248 pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
251 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
252 // clear dirty bit if write through
253 if (pkt->needsResponse())
254 respond(pkt, curTick+lat);
260 if (!pkt->req->isUncacheable()) {
261 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
262 /** @todo Move miss count code into BaseCache */
266 exitSimLoop("A cache reached the maximum miss count");
269 missQueue->handleMiss(pkt, size, curTick + hitLatency);
270 // return MA_CACHE_MISS;
275 template<class TagStore, class Buffering, class Coherence>
277 Cache<TagStore,Buffering,Coherence>::getPacket()
279 Packet * pkt = missQueue->getPacket();
281 if (!pkt->req->isUncacheable()) {
282 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
283 BlkType *blk = tags->findBlock(pkt);
284 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
285 (blk)? blk->status : 0);
286 missQueue->setBusCmd(pkt, cmd);
290 assert(!doMasterRequest() || missQueue->havePending());
291 assert(!pkt || pkt->time <= curTick);
295 template<class TagStore, class Buffering, class Coherence>
297 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
300 missQueue->markInService(pkt);
301 //Temp Hack for UPGRADES
302 if (pkt->cmd == Packet::UpgradeReq) {
305 } else if (pkt && !pkt->req->isUncacheable()) {
306 missQueue->restoreOrigCmd(pkt);
310 template<class TagStore, class Buffering, class Coherence>
312 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
315 if (pkt->senderState) {
316 // MemDebug::cacheResponse(pkt);
317 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
318 pkt->getAddr() & (((ULL(1))<<48)-1));
320 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
321 blk = tags->findBlock(pkt);
322 CacheBlk::State old_state = (blk) ? blk->status : 0;
323 PacketList writebacks;
324 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
325 coherence->getNewState(pkt,old_state),
327 while (!writebacks.empty()) {
328 missQueue->doWriteback(writebacks.front());
329 writebacks.pop_front();
332 missQueue->handleResponse(pkt, curTick + hitLatency);
336 template<class TagStore, class Buffering, class Coherence>
338 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
340 // Need to temporarily move this blk into MSHRs
341 MSHR *mshr = missQueue->allocateTargetList(addr);
344 // Read the data into the mshr
345 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
346 assert(dummy.empty());
347 assert(mshr->pkt->flags & SATISFIED);
348 // can overload order since it isn't used on non pending blocks
349 mshr->order = blk->status;
350 // temporarily remove the block from the cache.
351 tags->invalidateBlk(addr);
354 template<class TagStore, class Buffering, class Coherence>
356 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
358 // Need to temporarily move this blk into MSHRs
359 assert(mshr->pkt->cmd == Packet::ReadReq);
362 // Read the data into the mshr
363 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
364 assert(dummy.empty());
365 assert(mshr->pkt->flags & SATISFIED);
366 // can overload order since it isn't used on non pending blocks
367 mshr->order = blk->status;
368 // temporarily remove the block from the cache.
369 tags->invalidateBlk(mshr->pkt->getAddr());
373 template<class TagStore, class Buffering, class Coherence>
375 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
377 return coherence->getPacket();
381 template<class TagStore, class Buffering, class Coherence>
383 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
385 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
386 BlkType *blk = tags->findBlock(pkt);
387 MSHR *mshr = missQueue->findMSHR(blk_addr);
388 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
389 //If we find an mshr, and it is in service, we need to NACK or invalidate
391 if (mshr->inService) {
392 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
393 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
394 //If the outstanding request was an invalidate (upgrade,readex,..)
395 //Then we need to ACK the request until we get the data
396 //Also NACK if the outstanding request is not a cachefill (writeback)
397 pkt->flags |= SATISFIED;
398 pkt->flags |= NACKED_LINE;
399 assert("Don't detect these on the other side yet\n");
400 respondToSnoop(pkt, curTick + hitLatency);
404 //The supplier will be someone else, because we are waiting for
405 //the data. This should cause this cache to be forced to go to
406 //the shared state, not the exclusive even though the shared line
407 //won't be asserted. But for now we will just invlidate ourselves
408 //and allow the other cache to go into the exclusive state.
409 //@todo Make it so a read to a pending read doesn't invalidate.
410 //@todo Make it so that a read to a pending read can't be exclusive now.
412 //Set the address so find match works
413 assert("Don't have invalidates yet\n");
414 invalidatePkt->addrOverride(pkt->getAddr());
416 //Append the invalidate on
417 missQueue->addTarget(mshr,invalidatePkt);
418 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
423 //We also need to check the writeback buffers and handle those
424 std::vector<MSHR *> writebacks;
425 if (missQueue->findWrites(blk_addr, writebacks)) {
426 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
428 //Look through writebacks for any non-uncachable writes, use that
429 for (int i=0; i<writebacks.size(); i++) {
430 mshr = writebacks[i];
432 if (!mshr->pkt->req->isUncacheable()) {
434 //Only Upgrades don't get here
436 pkt->flags |= SATISFIED;
438 //If we are in an exclusive protocol, make it ask again
439 //to get write permissions (upgrade), signal shared
440 pkt->flags |= SHARED_LINE;
442 assert(pkt->isRead());
443 Addr offset = pkt->getAddr() & ~(blkSize - 1);
444 assert(offset < blkSize);
445 assert(pkt->getSize() <= blkSize);
446 assert(offset + pkt->getSize() <=blkSize);
447 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
449 respondToSnoop(pkt, curTick + hitLatency);
452 if (pkt->isInvalidate()) {
453 //This must be an upgrade or other cache will take ownership
454 missQueue->markInService(mshr->pkt);
461 CacheBlk::State new_state;
462 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
464 tags->handleSnoop(blk, new_state, pkt);
465 respondToSnoop(pkt, curTick + hitLatency);
468 tags->handleSnoop(blk, new_state);
471 template<class TagStore, class Buffering, class Coherence>
473 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
475 //Need to handle the response, if NACKED
476 if (pkt->flags & NACKED_LINE) {
477 //Need to mark it as not in service, and retry for bus
478 assert(0); //Yeah, we saw a NACK come through
480 //For now this should never get called, we return false when we see a NACK
481 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
482 //For now it retrys in just 2 cycles, need to figure out how to change that
483 //Eventually we will want to also have success come in as a parameter
484 //Need to make sure that we handle the functionality that happens on successufl
485 //return of the sendAddr function
489 template<class TagStore, class Buffering, class Coherence>
491 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
493 tags->invalidateBlk(addr);
498 * @todo Fix to not assume write allocate
500 template<class TagStore, class Buffering, class Coherence>
502 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
504 // MemDebug::cacheProbe(pkt);
505 if (!pkt->req->isUncacheable()) {
506 if (pkt->isInvalidate() && !pkt->isRead()
507 && !pkt->isWrite()) {
508 //Upgrade or Invalidate, satisfy it, don't forward
509 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
510 pkt->getAddr() & (((ULL(1))<<48)-1),
511 pkt->getAddr() & ~((Addr)blkSize - 1));
512 pkt->flags |= SATISFIED;
517 PacketList writebacks;
519 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
522 // Need to check for outstanding misses and writes
523 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
525 // There can only be one matching outstanding miss.
526 MSHR* mshr = missQueue->findMSHR(blk_addr);
528 // There can be many matching outstanding writes.
529 std::vector<MSHR*> writes;
530 missQueue->findWrites(blk_addr, writes);
533 otherSidePort->sendFunctional(pkt);
535 // Check for data in MSHR and writebuffer.
537 warn("Found outstanding miss on an non-update probe");
538 MSHR::TargetList *targets = mshr->getTargetList();
539 MSHR::TargetList::iterator i = targets->begin();
540 MSHR::TargetList::iterator end = targets->end();
541 for (; i != end; ++i) {
542 Packet * target = *i;
543 // If the target contains data, and it overlaps the
544 // probed request, need to update data
545 if (target->isWrite() && target->intersect(pkt)) {
549 if (target->getAddr() < pkt->getAddr()) {
550 int offset = pkt->getAddr() - target->getAddr();
551 pkt_data = pkt->getPtr<uint8_t>();
552 write_data = target->getPtr<uint8_t>() + offset;
553 data_size = target->getSize() - offset;
554 assert(data_size > 0);
555 if (data_size > pkt->getSize())
556 data_size = pkt->getSize();
558 int offset = target->getAddr() - pkt->getAddr();
559 pkt_data = pkt->getPtr<uint8_t>() + offset;
560 write_data = target->getPtr<uint8_t>();
561 data_size = pkt->getSize() - offset;
562 assert(data_size > pkt->getSize());
563 if (data_size > target->getSize())
564 data_size = target->getSize();
567 if (pkt->isWrite()) {
568 memcpy(pkt_data, write_data, data_size);
570 memcpy(write_data, pkt_data, data_size);
575 for (int i = 0; i < writes.size(); ++i) {
576 Packet * write = writes[i]->pkt;
577 if (write->intersect(pkt)) {
578 warn("Found outstanding write on an non-update probe");
582 if (write->getAddr() < pkt->getAddr()) {
583 int offset = pkt->getAddr() - write->getAddr();
584 pkt_data = pkt->getPtr<uint8_t>();
585 write_data = write->getPtr<uint8_t>() + offset;
586 data_size = write->getSize() - offset;
587 assert(data_size > 0);
588 if (data_size > pkt->getSize())
589 data_size = pkt->getSize();
591 int offset = write->getAddr() - pkt->getAddr();
592 pkt_data = pkt->getPtr<uint8_t>() + offset;
593 write_data = write->getPtr<uint8_t>();
594 data_size = pkt->getSize() - offset;
595 assert(data_size > pkt->getSize());
596 if (data_size > write->getSize())
597 data_size = write->getSize();
600 if (pkt->isWrite()) {
601 memcpy(pkt_data, write_data, data_size);
603 memcpy(write_data, pkt_data, data_size);
610 // update the cache state and statistics
611 if (mshr || !writes.empty()){
612 // Can't handle it, return pktuest unsatisfied.
615 if (!pkt->req->isUncacheable()) {
616 // Fetch the cache block to fill
617 BlkType *blk = tags->findBlock(pkt);
618 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
619 (blk)? blk->status : 0);
621 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
625 busPkt->time = curTick;
627 lat = memSidePort->sendAtomic(busPkt);
629 //Be sure to flip the response to a request for coherence
630 busPkt->makeAtomicResponse();
632 /* if (!(busPkt->flags & SATISFIED)) {
633 // blocked at a higher level, just return
637 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
639 CacheBlk::State old_state = (blk) ? blk->status : 0;
640 tags->handleFill(blk, busPkt,
641 coherence->getNewState(busPkt, old_state),
643 // Handle writebacks if needed
644 while (!writebacks.empty()){
645 memSidePort->sendAtomic(writebacks.front());
646 writebacks.pop_front();
648 return lat + hitLatency;
650 return memSidePort->sendAtomic(pkt);
654 // There was a cache hit.
655 // Handle writebacks if needed
656 while (!writebacks.empty()){
657 memSidePort->sendAtomic(writebacks.front());
658 writebacks.pop_front();
662 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
663 } else if (pkt->isWrite()) {
664 // Still need to change data in all locations.
665 return otherSidePort->sendAtomic(pkt);
667 return curTick + lat;
669 fatal("Probe not handled.\n");
673 template<class TagStore, class Buffering, class Coherence>
675 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
677 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
678 BlkType *blk = tags->findBlock(pkt);
679 MSHR *mshr = missQueue->findMSHR(blk_addr);
680 CacheBlk::State new_state = 0;
681 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
683 tags->handleSnoop(blk, new_state, pkt);
686 tags->handleSnoop(blk, new_state);