src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_events.hh" // for SimExitEvent
  55
  56 using namespace std;
  57
  58 template<class TagStore, class Buffering, class Coherence>
  59 bool
  60 Cache<TagStore,Buffering,Coherence>::
  61 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  62 {
  63     if (isCpuSide)
  64     {
  65         access(pkt);
  66     }
  67     else
  68     {
  69         if (pkt->isResponse())
  70             handleResponse(pkt);
  71         else
  72             snoop(pkt);
  73     }
  74     return true; //Deal with blocking....
  75 }
  76
  77 template<class TagStore, class Buffering, class Coherence>
  78 Tick
  79 Cache<TagStore,Buffering,Coherence>::
  80 doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  81 {
  82     if (isCpuSide)
  83     {
  84         probe(pkt, true);
  85     }
  86     else
  87     {
  88         if (pkt->isResponse())
  89             handleResponse(pkt);
  90         else
  91             snoopProbe(pkt, true);
  92     }
  93 }
  94
  95 template<class TagStore, class Buffering, class Coherence>
  96 void
  97 Cache<TagStore,Buffering,Coherence>::
  98 doFunctionalAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  99 {
 100     if (isCpuSide)
 101     {
 102         probe(pkt, false);
 103     }
 104     else
 105     {
 106         if (pkt->isResponse())
 107             handleResponse(pkt);
 108         else
 109             snoopProbe(pkt, false);
 110     }
 111 }
 112
 113 template<class TagStore, class Buffering, class Coherence>
 114 void
 115 Cache<TagStore,Buffering,Coherence>::
 116 recvStatusChange(Port::Status status, bool isCpuSide)
 117 {
 118
 119 }
 120
 121
 122 template<class TagStore, class Buffering, class Coherence>
 123 Cache<TagStore,Buffering,Coherence>::
 124 Cache(const std::string &_name,
 125       Cache<TagStore,Buffering,Coherence>::Params &params)
 126     : BaseCache(_name, params.baseParams),
 127       prefetchAccess(params.prefetchAccess),
 128       tags(params.tags), missQueue(params.missQueue),
 129       coherence(params.coherence), prefetcher(params.prefetcher),
 130       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
 131 {
 132     if (params.in == NULL) {
 133         topLevelCache = true;
 134     }
 135     tags->setCache(this, params.out->width, params.out->clockRate);
 136     tags->setPrefetcher(prefetcher);
 137     missQueue->setCache(this);
 138     missQueue->setPrefetcher(prefetcher);
 139     coherence->setCache(this);
 140     prefetcher->setCache(this);
 141     prefetcher->setTags(tags);
 142     prefetcher->setBuffer(missQueue);
 143     invalidatePkt = new Packet;
 144     invalidatePkt->cmd = Packet::InvalidateReq;
 145 }
 146
 147 template<class TagStore, class Buffering, class Coherence>
 148 void
 149 Cache<TagStore,Buffering,Coherence>::regStats()
 150 {
 151     BaseCache::regStats();
 152     tags->regStats(name());
 153     missQueue->regStats(name());
 154     coherence->regStats(name());
 155     prefetcher->regStats(name());
 156 }
 157
 158 template<class TagStore, class Buffering, class Coherence>
 159 bool
 160 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 161 {
 162 //@todo Add back in MemDebug Calls
 163 //    MemDebug::cacheAccess(pkt);
 164     BlkType *blk = NULL;
 165     PacketList writebacks;
 166     int size = blkSize;
 167     int lat = hitLatency;
 168     if (prefetchAccess) {
 169         //We are determining prefetches on access stream, call prefetcher
 170         prefetcher->handleMiss(pkt, curTick);
 171     }
 172     if (!pkt->req->isUncacheable()) {
 173         if (pkt->isInvalidate() && !pkt->isRead()
 174             && !pkt->isWrite()) {
 175             //Upgrade or Invalidate
 176             //Look into what happens if two slave caches on bus
 177             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 178                     pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1),
 179                     pkt->addr & ~((Addr)blkSize - 1));
 180
 181             //@todo Should this return latency have the hit latency in it?
 182 //          respond(pkt,curTick+lat);
 183             (int)pkt->coherence |= SATISFIED;
 184 //            return MA_HIT; //@todo, return values
 185             return true;
 186         }
 187         blk = tags->handleAccess(pkt, lat, writebacks);
 188     } else {
 189         size = pkt->size;
 190     }
 191     // If this is a block size write/hint (WH64) allocate the block here
 192     // if the coherence protocol allows it.
 193     /** @todo make the fast write alloc (wh64) work with coherence. */
 194     /** @todo Do we want to do fast writes for writebacks as well? */
 195     if (!blk && pkt->size >= blkSize && coherence->allowFastWrites() &&
 196         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 197         // not outstanding misses, can do this
 198         MSHR* outstanding_miss = missQueue->findMSHR(pkt->addr, pkt->req->asid);
 199         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 200             if (outstanding_miss) {
 201                 warn("WriteInv doing a fastallocate"
 202                      "with an outstanding miss to the same address\n");
 203             }
 204             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 205                                    writebacks);
 206             ++fastWrites;
 207         }
 208     }
 209     while (!writebacks.empty()) {
 210         missQueue->doWriteback(writebacks.front());
 211         writebacks.pop_front();
 212     }
 213     DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
 214             pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 215             pkt->addr & ~((Addr)blkSize - 1), pkt->req->pc);
 216     if (blk) {
 217         // Hit
 218         hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 219         // clear dirty bit if write through
 220         if (pkt->needsResponse())
 221             respond(pkt, curTick+lat);
 222 //      return MA_HIT;
 223         return true;
 224     }
 225
 226     // Miss
 227     if (!pkt->req->isUncacheable()) {
 228         misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 229         /** @todo Move miss count code into BaseCache */
 230         if (missCount) {
 231             --missCount;
 232             if (missCount == 0)
 233                 new SimLoopExitEvent("A cache reached the maximum miss count");
 234         }
 235     }
 236     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 237 //    return MA_CACHE_MISS;
 238     return true;
 239 }
 240
 241
 242 template<class TagStore, class Buffering, class Coherence>
 243 Packet *
 244 Cache<TagStore,Buffering,Coherence>::getPacket()
 245 {
 246     Packet * pkt = missQueue->getPacket();
 247     if (pkt) {
 248         if (!pkt->req->isUncacheable()) {
 249             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
 250             BlkType *blk = tags->findBlock(pkt);
 251             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 252                                               (blk)? blk->status : 0);
 253             missQueue->setBusCmd(pkt, cmd);
 254         }
 255     }
 256
 257     assert(!doMasterRequest() || missQueue->havePending());
 258     assert(!pkt || pkt->time <= curTick);
 259     return pkt;
 260 }
 261
 262 template<class TagStore, class Buffering, class Coherence>
 263 void
 264 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
 265 {
 266     if (success) {
 267         missQueue->markInService(pkt);
 268           //Temp Hack for UPGRADES
 269           if (pkt->cmd == Packet::UpgradeReq) {
 270               handleResponse(pkt);
 271           }
 272     } else if (pkt && !pkt->req->isUncacheable()) {
 273         missQueue->restoreOrigCmd(pkt);
 274     }
 275 }
 276
 277 template<class TagStore, class Buffering, class Coherence>
 278 void
 279 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 280 {
 281     BlkType *blk = NULL;
 282     if (pkt->senderState) {
 283 //      MemDebug::cacheResponse(pkt);
 284         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->addr,
 285                 pkt->addr & (((ULL(1))<<48)-1));
 286
 287         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 288             blk = tags->findBlock(pkt);
 289             CacheBlk::State old_state = (blk) ? blk->status : 0;
 290             PacketList writebacks;
 291             blk = tags->handleFill(blk, pkt->senderState,
 292                                    coherence->getNewState(pkt,old_state),
 293                                    writebacks);
 294             while (!writebacks.empty()) {
 295                     missQueue->doWriteback(writebacks.front());
 296             }
 297         }
 298         missQueue->handleResponse(pkt, curTick + hitLatency);
 299     }
 300 }
 301
 302 template<class TagStore, class Buffering, class Coherence>
 303 void
 304 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr, int asid)
 305 {
 306     // Need to temporarily move this blk into MSHRs
 307     MSHR *mshr = missQueue->allocateTargetList(addr, asid);
 308     int lat;
 309     PacketList dummy;
 310     // Read the data into the mshr
 311     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 312     assert(dummy.empty());
 313     assert((int)mshr->pkt->coherence & SATISFIED);
 314     // can overload order since it isn't used on non pending blocks
 315     mshr->order = blk->status;
 316     // temporarily remove the block from the cache.
 317     tags->invalidateBlk(addr, asid);
 318 }
 319
 320 template<class TagStore, class Buffering, class Coherence>
 321 void
 322 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 323 {
 324     // Need to temporarily move this blk into MSHRs
 325     assert(mshr->pkt->cmd == Packet::ReadReq);
 326     int lat;
 327     PacketList dummy;
 328     // Read the data into the mshr
 329     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 330     assert(dummy.empty());
 331     assert((int)mshr->pkt->coherence & SATISFIED);
 332     // can overload order since it isn't used on non pending blocks
 333     mshr->order = blk->status;
 334     // temporarily remove the block from the cache.
 335     tags->invalidateBlk(mshr->pkt->addr, mshr->pkt->req->asid);
 336 }
 337
 338
 339 template<class TagStore, class Buffering, class Coherence>
 340 Packet *
 341 Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
 342 {
 343     return coherence->getPacket();
 344 }
 345
 346
 347 template<class TagStore, class Buffering, class Coherence>
 348 void
 349 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 350 {
 351     Addr blk_addr = pkt->addr & ~(Addr(blkSize-1));
 352     BlkType *blk = tags->findBlock(pkt);
 353     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
 354     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 355         //If we find an mshr, and it is in service, we need to NACK or invalidate
 356         if (mshr) {
 357             if (mshr->inService) {
 358                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 359                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 360                     //If the outstanding request was an invalidate (upgrade,readex,..)
 361                     //Then we need to ACK the request until we get the data
 362                     //Also NACK if the outstanding request is not a cachefill (writeback)
 363                     (int)pkt->coherence |= NACKED_LINE;
 364                     return;
 365                 }
 366                 else {
 367                     //The supplier will be someone else, because we are waiting for
 368                     //the data.  This should cause this cache to be forced to go to
 369                     //the shared state, not the exclusive even though the shared line
 370                     //won't be asserted.  But for now we will just invlidate ourselves
 371                     //and allow the other cache to go into the exclusive state.
 372                     //@todo Make it so a read to a pending read doesn't invalidate.
 373                     //@todo Make it so that a read to a pending read can't be exclusive now.
 374
 375                     //Set the address so find match works
 376                     invalidatePkt->addr = pkt->addr;
 377
 378                     //Append the invalidate on
 379                     missQueue->addTarget(mshr,invalidatePkt);
 380                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->addr & (((ULL(1))<<48)-1));
 381                     return;
 382                 }
 383             }
 384         }
 385         //We also need to check the writeback buffers and handle those
 386         std::vector<MSHR *> writebacks;
 387         if (missQueue->findWrites(blk_addr, pkt->req->asid, writebacks)) {
 388             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->addr & (((ULL(1))<<48)-1));
 389
 390             //Look through writebacks for any non-uncachable writes, use that
 391             for (int i=0; i<writebacks.size(); i++) {
 392                 mshr = writebacks[i];
 393
 394                 if (!mshr->pkt->req->isUncacheable()) {
 395                     if (pkt->isRead()) {
 396                         //Only Upgrades don't get here
 397                         //Supply the data
 398                         (int)pkt->coherence |= SATISFIED;
 399
 400                         //If we are in an exclusive protocol, make it ask again
 401                         //to get write permissions (upgrade), signal shared
 402                         (int)pkt->coherence |= SHARED_LINE;
 403
 404                         assert(pkt->isRead());
 405                         assert(pkt->offset < blkSize);
 406                         assert(pkt->size <= blkSize);
 407                         assert(pkt->offset + pkt->size <=blkSize);
 408                         memcpy(pkt->data, mshr->pkt->data + pkt->offset, pkt->size);
 409
 410                         respondToSnoop(pkt);
 411                     }
 412
 413                     if (pkt->isInvalidate()) {
 414                         //This must be an upgrade or other cache will take ownership
 415                         missQueue->markInService(mshr->pkt);
 416                     }
 417                     return;
 418                 }
 419             }
 420         }
 421     }
 422     CacheBlk::State new_state;
 423     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 424     if (satisfy) {
 425         tags->handleSnoop(blk, new_state, pkt);
 426         respondToSnoop(pkt);
 427         return;
 428     }
 429     tags->handleSnoop(blk, new_state);
 430 }
 431
 432 template<class TagStore, class Buffering, class Coherence>
 433 void
 434 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 435 {
 436     //Need to handle the response, if NACKED
 437     if ((int)pkt->coherence & NACKED_LINE) {
 438         //Need to mark it as not in service, and retry for bus
 439         assert(0); //Yeah, we saw a NACK come through
 440
 441         //For now this should never get called, we return false when we see a NACK
 442         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 443         //For now it retrys in just 2 cycles, need to figure out how to change that
 444         //Eventually we will want to also have success come in as a parameter
 445         //Need to make sure that we handle the functionality that happens on successufl
 446         //return of the sendAddr function
 447     }
 448 }
 449
 450 template<class TagStore, class Buffering, class Coherence>
 451 void
 452 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr, int asid)
 453 {
 454     tags->invalidateBlk(addr,asid);
 455 }
 456
 457
 458 /**
 459  * @todo Fix to not assume write allocate
 460  */
 461 template<class TagStore, class Buffering, class Coherence>
 462 Tick
 463 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 464 {
 465 //    MemDebug::cacheProbe(pkt);
 466
 467     if (!pkt->req->isUncacheable()) {
 468         if (pkt->isInvalidate() && !pkt->isRead()
 469             && !pkt->isWrite()) {
 470             //Upgrade or Invalidate, satisfy it, don't forward
 471             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 472                     pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1),
 473                     pkt->addr & ~((Addr)blkSize - 1));
 474             (int)pkt->coherence |= SATISFIED;
 475             return 0;
 476         }
 477     }
 478
 479     if (!update && !doData()) {
 480         // Nothing to do here
 481         return mi->sendProbe(pkt,update);
 482     }
 483
 484     PacketList writebacks;
 485     int lat;
 486     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 487
 488     if (!blk) {
 489         // Need to check for outstanding misses and writes
 490         Addr blk_addr = pkt->addr & ~(blkSize - 1);
 491
 492         // There can only be one matching outstanding miss.
 493         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
 494
 495         // There can be many matching outstanding writes.
 496         vector<MSHR*> writes;
 497         missQueue->findWrites(blk_addr, pkt->req->asid, writes);
 498
 499         if (!update) {
 500             mi->sendProbe(pkt, update);
 501             // Check for data in MSHR and writebuffer.
 502             if (mshr) {
 503                 warn("Found outstanding miss on an non-update probe");
 504                 MSHR::TargetList *targets = mshr->getTargetList();
 505                 MSHR::TargetList::iterator i = targets->begin();
 506                 MSHR::TargetList::iterator end = targets->end();
 507                 for (; i != end; ++i) {
 508                     Packet * target = *i;
 509                     // If the target contains data, and it overlaps the
 510                     // probed request, need to update data
 511                     if (target->isWrite() && target->overlaps(pkt)) {
 512                         uint8_t* pkt_data;
 513                         uint8_t* write_data;
 514                         int data_size;
 515                         if (target->addr < pkt->addr) {
 516                             int offset = pkt->addr - target->paddr;
 517                             pkt_data = pkt->data;
 518                             write_data = target->data + offset;
 519                             data_size = target->size - offset;
 520                             assert(data_size > 0);
 521                             if (data_size > pkt->size)
 522                                 data_size = pkt->size;
 523                         } else {
 524                             int offset = target->addr - pkt->addr;
 525                             pkt_data = pkt->data + offset;
 526                             write_data = target->data;
 527                             data_size = pkt->size - offset;
 528                             assert(data_size > pkt->size);
 529                             if (data_size > target->size)
 530                                 data_size = target->size;
 531                         }
 532
 533                         if (pkt->isWrite()) {
 534                             memcpy(pkt_data, write_data, data_size);
 535                         } else {
 536                             memcpy(write_data, pkt_data, data_size);
 537                         }
 538                     }
 539                 }
 540             }
 541             for (int i = 0; i < writes.size(); ++i) {
 542                 Packet * write = writes[i]->pkt;
 543                 if (write->overlaps(pkt)) {
 544                     warn("Found outstanding write on an non-update probe");
 545                     uint8_t* pkt_data;
 546                     uint8_t* write_data;
 547                     int data_size;
 548                     if (write->addr < pkt->addr) {
 549                         int offset = pkt->addr - write->addr;
 550                         pkt_data = pkt->data;
 551                         write_data = write->data + offset;
 552                         data_size = write->size - offset;
 553                         assert(data_size > 0);
 554                         if (data_size > pkt->size)
 555                             data_size = pkt->size;
 556                     } else {
 557                         int offset = write->addr - pkt->addr;
 558                         pkt_data = pkt->data + offset;
 559                         write_data = write->data;
 560                         data_size = pkt->size - offset;
 561                         assert(data_size > pkt->size);
 562                         if (data_size > write->size)
 563                             data_size = write->size;
 564                     }
 565
 566                     if (pkt->isWrite()) {
 567                         memcpy(pkt_data, write_data, data_size);
 568                     } else {
 569                         memcpy(write_data, pkt_data, data_size);
 570                     }
 571
 572                 }
 573             }
 574             return 0;
 575         } else {
 576             // update the cache state and statistics
 577             if (mshr || !writes.empty()){
 578                 // Can't handle it, return pktuest unsatisfied.
 579                 return 0;
 580             }
 581             if (!pkt->req->isUncacheable()) {
 582                 // Fetch the cache block to fill
 583                 Packet * busPkt = new Packet();
 584                 busPkt->addr = blk_addr;
 585                 busPkt->size = blkSize;
 586                 busPkt->data = new uint8_t[blkSize];
 587
 588                 BlkType *blk = tags->findBlock(pkt);
 589                 busPkt->cmd = coherence->getBusCmd(pkt->cmd,
 590                                                    (blk)? blk->status : 0);
 591
 592                 busPkt->req->asid = pkt->req->asid;
 593                 busPkt->xc = pkt->xc;
 594                 busPkt->req->setThreadNum() = pkt->req->getThreadNum();
 595                 busPkt->time = curTick;
 596
 597                 lat = mi->sendProbe(busPkt, update);
 598
 599                 if (!busPkt->isSatisfied()) {
 600                     // blocked at a higher level, just return
 601                     return 0;
 602                 }
 603
 604                 misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 605
 606                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 607                 tags->handleFill(blk, busPkt,
 608                                  coherence->getNewState(busPkt, old_state),
 609                                  writebacks, pkt);
 610                 // Handle writebacks if needed
 611                 while (!writebacks.empty()){
 612                     mi->sendProbe(writebacks.front(), update);
 613                     writebacks.pop_front();
 614                 }
 615                 return lat + hitLatency;
 616             } else {
 617                 return mi->sendProbe(pkt,update);
 618             }
 619         }
 620     } else {
 621         // There was a cache hit.
 622         // Handle writebacks if needed
 623         while (!writebacks.empty()){
 624             mi->sendProbe(writebacks.front(), update);
 625             writebacks.pop_front();
 626         }
 627
 628         if (update) {
 629             hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 630         } else if (pkt->isWrite()) {
 631             // Still need to change data in all locations.
 632             return mi->sendProbe(pkt, update);
 633         }
 634         return curTick + lat;
 635     }
 636     fatal("Probe not handled.\n");
 637     return 0;
 638 }
 639
 640 template<class TagStore, class Buffering, class Coherence>
 641 Tick
 642 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
 643 {
 644     Addr blk_addr = pkt->addr & ~(Addr(blkSize-1));
 645     BlkType *blk = tags->findBlock(pkt);
 646     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
 647     CacheBlk::State new_state = 0;
 648     bool satisfy = coherence->handleBusPktuest(pkt,blk,mshr, new_state);
 649     if (satisfy) {
 650         tags->handleSnoop(blk, new_state, pkt);
 651         return hitLatency;
 652     }
 653     tags->handleSnoop(blk, new_state);
 654     return 0;
 655 }
 656