2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->isLocked())) {
64 pkt->req->setScResult(1);
71 if (pkt->isResponse())
74 //Check if we should do the snoop
75 if (pkt->flags & SNOOP_COMMIT)
82 template<class TagStore, class Buffering, class Coherence>
84 Cache<TagStore,Buffering,Coherence>::
85 doAtomicAccess(Packet *pkt, bool isCpuSide)
89 probe(pkt, true, NULL);
90 //TEMP ALWAYS SUCCES FOR NOW
91 pkt->result = Packet::Success;
95 if (pkt->isResponse())
98 return snoopProbe(pkt);
100 //Fix this timing info
104 template<class TagStore, class Buffering, class Coherence>
106 Cache<TagStore,Buffering,Coherence>::
107 doFunctionalAccess(Packet *pkt, bool isCpuSide)
111 //TEMP USE CPU?THREAD 0 0
112 pkt->req->setThreadContext(0,0);
114 probe(pkt, false, memSidePort);
115 //TEMP ALWAYS SUCCESFUL FOR NOW
116 pkt->result = Packet::Success;
120 probe(pkt, false, cpuSidePort);
124 template<class TagStore, class Buffering, class Coherence>
126 Cache<TagStore,Buffering,Coherence>::
127 recvStatusChange(Port::Status status, bool isCpuSide)
133 template<class TagStore, class Buffering, class Coherence>
134 Cache<TagStore,Buffering,Coherence>::
135 Cache(const std::string &_name,
136 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
137 : BaseCache(_name, params.baseParams),
138 prefetchAccess(params.prefetchAccess),
139 tags(params.tags), missQueue(params.missQueue),
140 coherence(params.coherence), prefetcher(params.prefetcher),
141 hitLatency(params.hitLatency)
143 tags->setCache(this);
144 tags->setPrefetcher(prefetcher);
145 missQueue->setCache(this);
146 missQueue->setPrefetcher(prefetcher);
147 coherence->setCache(this);
148 prefetcher->setCache(this);
149 prefetcher->setTags(tags);
150 prefetcher->setBuffer(missQueue);
151 invalidateReq = new Request((Addr) NULL, blkSize, 0);
152 invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
155 template<class TagStore, class Buffering, class Coherence>
157 Cache<TagStore,Buffering,Coherence>::regStats()
159 BaseCache::regStats();
160 tags->regStats(name());
161 missQueue->regStats(name());
162 coherence->regStats(name());
163 prefetcher->regStats(name());
166 template<class TagStore, class Buffering, class Coherence>
168 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
170 //@todo Add back in MemDebug Calls
171 // MemDebug::cacheAccess(pkt);
173 PacketList writebacks;
175 int lat = hitLatency;
176 if (prefetchAccess) {
177 //We are determining prefetches on access stream, call prefetcher
178 prefetcher->handleMiss(pkt, curTick);
180 if (!pkt->req->isUncacheable()) {
181 blk = tags->handleAccess(pkt, lat, writebacks);
183 size = pkt->getSize();
185 // If this is a block size write/hint (WH64) allocate the block here
186 // if the coherence protocol allows it.
187 /** @todo make the fast write alloc (wh64) work with coherence. */
188 /** @todo Do we want to do fast writes for writebacks as well? */
189 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
190 (pkt->cmd == Packet::WriteReq
191 || pkt->cmd == Packet::WriteInvalidateReq) ) {
192 // not outstanding misses, can do this
193 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
194 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
195 if (outstanding_miss) {
196 warn("WriteInv doing a fastallocate"
197 "with an outstanding miss to the same address\n");
199 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
204 while (!writebacks.empty()) {
205 missQueue->doWriteback(writebacks.front());
206 writebacks.pop_front();
208 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
209 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
210 pkt->getAddr() & ~((Addr)blkSize - 1));
213 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
214 // clear dirty bit if write through
215 if (pkt->needsResponse())
216 respond(pkt, curTick+lat);
217 if (pkt->cmd == Packet::Writeback) {
218 //Signal that you can kill the pkt/req
219 pkt->flags |= SATISFIED;
225 if (!pkt->req->isUncacheable()) {
226 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
227 /** @todo Move miss count code into BaseCache */
231 exitSimLoop("A cache reached the maximum miss count");
234 missQueue->handleMiss(pkt, size, curTick + hitLatency);
235 // return MA_CACHE_MISS;
240 template<class TagStore, class Buffering, class Coherence>
242 Cache<TagStore,Buffering,Coherence>::getPacket()
244 assert(missQueue->havePending());
245 Packet * pkt = missQueue->getPacket();
247 if (!pkt->req->isUncacheable()) {
248 if (pkt->cmd == Packet::HardPFReq)
249 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
250 BlkType *blk = tags->findBlock(pkt);
251 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
252 (blk)? blk->status : 0);
253 missQueue->setBusCmd(pkt, cmd);
257 assert(!doMasterRequest() || missQueue->havePending());
258 assert(!pkt || pkt->time <= curTick);
262 template<class TagStore, class Buffering, class Coherence>
264 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
267 if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
268 if (!mshr->pkt->needsResponse()
269 && !(mshr->pkt->cmd == Packet::UpgradeReq)
270 && (pkt && (pkt->flags & SATISFIED))) {
271 //Writeback, clean up the non copy version of the packet
274 missQueue->markInService(mshr->pkt, mshr);
275 //Temp Hack for UPGRADES
276 if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
277 assert(pkt); //Upgrades need to be fixed
278 pkt->flags &= ~CACHE_LINE_FILL;
279 BlkType *blk = tags->findBlock(pkt);
280 CacheBlk::State old_state = (blk) ? blk->status : 0;
281 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
282 if (old_state != new_state)
283 DPRINTF(Cache, "Block for blk addr %x moving from "
285 pkt->getAddr() & (((ULL(1))<<48)-1),
286 old_state, new_state);
287 //Set the state on the upgrade
288 memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
289 PacketList writebacks;
290 tags->handleFill(blk, mshr, new_state, writebacks, pkt);
291 assert(writebacks.empty());
292 missQueue->handleResponse(pkt, curTick + hitLatency);
294 } else if (pkt && !pkt->req->isUncacheable()) {
295 pkt->flags &= ~NACKED_LINE;
296 pkt->flags &= ~SATISFIED;
297 pkt->flags &= ~SNOOP_COMMIT;
299 //Rmove copy from mshr
303 missQueue->restoreOrigCmd(pkt);
307 template<class TagStore, class Buffering, class Coherence>
309 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
312 if (pkt->senderState) {
313 //Delete temp copy in MSHR, restore it.
314 delete ((MSHR*)pkt->senderState)->pkt;
315 ((MSHR*)pkt->senderState)->pkt = pkt;
316 if (pkt->result == Packet::Nacked) {
317 //pkt->reinitFromRequest();
318 warn("NACKs from devices not connected to the same bus "
319 "not implemented\n");
322 if (pkt->result == Packet::BadAddress) {
323 //Make the response a Bad address and send it
325 // MemDebug::cacheResponse(pkt);
326 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
327 pkt->getAddr() & (((ULL(1))<<48)-1));
329 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
330 blk = tags->findBlock(pkt);
331 CacheBlk::State old_state = (blk) ? blk->status : 0;
332 PacketList writebacks;
333 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
334 if (old_state != new_state)
335 DPRINTF(Cache, "Block for blk addr %x moving from "
337 pkt->getAddr() & (((ULL(1))<<48)-1),
338 old_state, new_state);
339 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
340 new_state, writebacks, pkt);
341 while (!writebacks.empty()) {
342 missQueue->doWriteback(writebacks.front());
343 writebacks.pop_front();
346 missQueue->handleResponse(pkt, curTick + hitLatency);
350 template<class TagStore, class Buffering, class Coherence>
352 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
354 return coherence->getPacket();
357 template<class TagStore, class Buffering, class Coherence>
359 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
363 coherence->sendResult(pkt, cshr, success);
367 template<class TagStore, class Buffering, class Coherence>
369 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
371 if (pkt->req->isUncacheable()) {
372 //Can't get a hit on an uncacheable address
373 //Revisit this for multi level coherence
377 //Send a timing (true) invalidate up if the protocol calls for it
378 coherence->propogateInvalidate(pkt, true);
380 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
381 BlkType *blk = tags->findBlock(pkt);
382 MSHR *mshr = missQueue->findMSHR(blk_addr);
383 if (coherence->hasProtocol() || pkt->isInvalidate()) {
384 //@todo Move this into handle bus req
385 //If we find an mshr, and it is in service, we need to NACK or
388 if (mshr->inService) {
389 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
390 && (pkt->cmd != Packet::InvalidateReq
391 && pkt->cmd != Packet::WriteInvalidateReq)) {
392 //If the outstanding request was an invalidate
393 //(upgrade,readex,..) Then we need to ACK the request
394 //until we get the data Also NACK if the outstanding
395 //request is not a cachefill (writeback)
396 assert(!(pkt->flags & SATISFIED));
397 pkt->flags |= SATISFIED;
398 pkt->flags |= NACKED_LINE;
399 ///@todo NACK's from other levels
400 //warn("NACKs from devices not connected to the same bus "
401 //"not implemented\n");
402 //respondToSnoop(pkt, curTick + hitLatency);
406 //The supplier will be someone else, because we are
407 //waiting for the data. This should cause this cache to
408 //be forced to go to the shared state, not the exclusive
409 //even though the shared line won't be asserted. But for
410 //now we will just invlidate ourselves and allow the other
411 //cache to go into the exclusive state. @todo Make it so
412 //a read to a pending read doesn't invalidate. @todo Make
413 //it so that a read to a pending read can't be exclusive
416 //Set the address so find match works
417 //panic("Don't have invalidates yet\n");
418 invalidatePkt->addrOverride(pkt->getAddr());
420 //Append the invalidate on
421 missQueue->addTarget(mshr,invalidatePkt);
422 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n",
423 pkt->getAddr() & (((ULL(1))<<48)-1));
428 //We also need to check the writeback buffers and handle those
429 std::vector<MSHR *> writebacks;
430 if (missQueue->findWrites(blk_addr, writebacks)) {
431 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n",
432 pkt->getAddr() & (((ULL(1))<<48)-1));
434 //Look through writebacks for any non-uncachable writes, use that
435 for (int i=0; i<writebacks.size(); i++) {
436 mshr = writebacks[i];
438 if (!mshr->pkt->req->isUncacheable()) {
440 //Only Upgrades don't get here
442 assert(!(pkt->flags & SATISFIED));
443 pkt->flags |= SATISFIED;
445 //If we are in an exclusive protocol, make it ask again
446 //to get write permissions (upgrade), signal shared
447 pkt->flags |= SHARED_LINE;
449 assert(pkt->isRead());
450 Addr offset = pkt->getAddr() & (blkSize - 1);
451 assert(offset < blkSize);
452 assert(pkt->getSize() <= blkSize);
453 assert(offset + pkt->getSize() <=blkSize);
454 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
456 respondToSnoop(pkt, curTick + hitLatency);
459 if (pkt->isInvalidate()) {
460 //This must be an upgrade or other cache will take
462 missQueue->markInService(mshr->pkt, mshr);
469 CacheBlk::State new_state;
470 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
472 DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
473 "now supplying data, new state is %i\n",
474 pkt->cmdString(), blk_addr, new_state);
476 tags->handleSnoop(blk, new_state, pkt);
477 respondToSnoop(pkt, curTick + hitLatency);
481 DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
482 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
483 tags->handleSnoop(blk, new_state);
486 template<class TagStore, class Buffering, class Coherence>
488 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
490 //Need to handle the response, if NACKED
491 if (pkt->flags & NACKED_LINE) {
492 //Need to mark it as not in service, and retry for bus
493 assert(0); //Yeah, we saw a NACK come through
495 //For now this should never get called, we return false when we see a
496 //NACK instead, by doing this we allow the bus_blocked mechanism to
497 //handle the retry For now it retrys in just 2 cycles, need to figure
498 //out how to change that Eventually we will want to also have success
499 //come in as a parameter Need to make sure that we handle the
500 //functionality that happens on successufl return of the sendAddr
505 template<class TagStore, class Buffering, class Coherence>
507 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
509 tags->invalidateBlk(addr);
514 * @todo Fix to not assume write allocate
516 template<class TagStore, class Buffering, class Coherence>
518 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
519 CachePort* otherSidePort)
521 // MemDebug::cacheProbe(pkt);
522 if (!pkt->req->isUncacheable()) {
523 if (pkt->isInvalidate() && !pkt->isRead()
524 && !pkt->isWrite()) {
525 //Upgrade or Invalidate, satisfy it, don't forward
526 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
527 pkt->getAddr() & (((ULL(1))<<48)-1),
528 pkt->getAddr() & ~((Addr)blkSize - 1));
529 pkt->flags |= SATISFIED;
534 if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
535 // Still need to change data in all locations.
536 otherSidePort->sendFunctional(pkt);
537 if (pkt->isRead() && pkt->result == Packet::Success)
541 PacketList writebacks;
543 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
545 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
546 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
547 pkt->getAddr() & ~((Addr)blkSize - 1));
550 // Need to check for outstanding misses and writes
551 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
553 // There can only be one matching outstanding miss.
554 MSHR* mshr = missQueue->findMSHR(blk_addr);
556 // There can be many matching outstanding writes.
557 std::vector<MSHR*> writes;
558 missQueue->findWrites(blk_addr, writes);
561 // Check for data in MSHR and writebuffer.
563 warn("Found outstanding miss on an non-update probe");
564 MSHR::TargetList *targets = mshr->getTargetList();
565 MSHR::TargetList::iterator i = targets->begin();
566 MSHR::TargetList::iterator end = targets->end();
567 for (; i != end; ++i) {
568 Packet * target = *i;
569 // If the target contains data, and it overlaps the
570 // probed request, need to update data
571 if (target->isWrite() && target->intersect(pkt)) {
575 if (target->getAddr() < pkt->getAddr()) {
576 int offset = pkt->getAddr() - target->getAddr();
577 pkt_data = pkt->getPtr<uint8_t>();
578 write_data = target->getPtr<uint8_t>() + offset;
579 data_size = target->getSize() - offset;
580 assert(data_size > 0);
581 if (data_size > pkt->getSize())
582 data_size = pkt->getSize();
584 int offset = target->getAddr() - pkt->getAddr();
585 pkt_data = pkt->getPtr<uint8_t>() + offset;
586 write_data = target->getPtr<uint8_t>();
587 data_size = pkt->getSize() - offset;
588 assert(data_size > pkt->getSize());
589 if (data_size > target->getSize())
590 data_size = target->getSize();
593 if (pkt->isWrite()) {
594 memcpy(pkt_data, write_data, data_size);
596 memcpy(write_data, pkt_data, data_size);
601 for (int i = 0; i < writes.size(); ++i) {
602 Packet * write = writes[i]->pkt;
603 if (write->intersect(pkt)) {
604 warn("Found outstanding write on an non-update probe");
608 if (write->getAddr() < pkt->getAddr()) {
609 int offset = pkt->getAddr() - write->getAddr();
610 pkt_data = pkt->getPtr<uint8_t>();
611 write_data = write->getPtr<uint8_t>() + offset;
612 data_size = write->getSize() - offset;
613 assert(data_size > 0);
614 if (data_size > pkt->getSize())
615 data_size = pkt->getSize();
617 int offset = write->getAddr() - pkt->getAddr();
618 pkt_data = pkt->getPtr<uint8_t>() + offset;
619 write_data = write->getPtr<uint8_t>();
620 data_size = pkt->getSize() - offset;
621 assert(data_size > pkt->getSize());
622 if (data_size > write->getSize())
623 data_size = write->getSize();
626 if (pkt->isWrite()) {
627 memcpy(pkt_data, write_data, data_size);
629 memcpy(write_data, pkt_data, data_size);
636 // update the cache state and statistics
637 if (mshr || !writes.empty()){
638 // Can't handle it, return pktuest unsatisfied.
639 panic("Atomic access ran into outstanding MSHR's or WB's!");
641 if (!pkt->req->isUncacheable()) {
642 // Fetch the cache block to fill
643 BlkType *blk = tags->findBlock(pkt);
644 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
645 (blk)? blk->status : 0);
647 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
651 busPkt->time = curTick;
653 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
655 busPkt->getAddr() & (((ULL(1))<<48)-1),
656 busPkt->getAddr() & ~((Addr)blkSize - 1));
658 lat = memSidePort->sendAtomic(busPkt);
660 //Be sure to flip the response to a request for coherence
661 if (busPkt->needsResponse()) {
662 busPkt->makeAtomicResponse();
665 /* if (!(busPkt->flags & SATISFIED)) {
666 // blocked at a higher level, just return
670 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
672 CacheBlk::State old_state = (blk) ? blk->status : 0;
673 CacheBlk::State new_state =
674 coherence->getNewState(busPkt, old_state);
676 "Receive response:%s for blk addr %x in state %i\n",
678 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
679 if (old_state != new_state)
680 DPRINTF(Cache, "Block for blk addr %x moving from "
682 busPkt->getAddr() & (((ULL(1))<<48)-1),
683 old_state, new_state);
685 tags->handleFill(blk, busPkt,
691 // Handle writebacks if needed
692 while (!writebacks.empty()){
693 Packet *wbPkt = writebacks.front();
694 memSidePort->sendAtomic(wbPkt);
695 writebacks.pop_front();
698 return lat + hitLatency;
700 return memSidePort->sendAtomic(pkt);
703 // There was a cache hit.
704 // Handle writebacks if needed
705 while (!writebacks.empty()){
706 memSidePort->sendAtomic(writebacks.front());
707 writebacks.pop_front();
710 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
714 fatal("Probe not handled.\n");
718 template<class TagStore, class Buffering, class Coherence>
720 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
722 //Send a atomic (false) invalidate up if the protocol calls for it
723 coherence->propogateInvalidate(pkt, false);
725 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
726 BlkType *blk = tags->findBlock(pkt);
727 MSHR *mshr = missQueue->findMSHR(blk_addr);
728 CacheBlk::State new_state = 0;
729 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
731 DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
732 "now supplying data, new state is %i\n",
733 pkt->cmdString(), blk_addr, new_state);
735 tags->handleSnoop(blk, new_state, pkt);
739 DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
741 pkt->cmdString(), blk_addr, new_state);
742 tags->handleSnoop(blk, new_state);