src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 bool SIGNAL_NACK_HACK;
  57
  58 template<class TagStore, class Buffering, class Coherence>
  59 bool
  60 Cache<TagStore,Buffering,Coherence>::
  61 doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
  62 {
  63     if (isCpuSide)
  64     {
  65         if (pkt->isWrite() && (pkt->req->isLocked())) {
  66             pkt->req->setScResult(1);
  67         }
  68         access(pkt);
  69
  70     }
  71     else
  72     {
  73         if (pkt->isResponse())
  74             handleResponse(pkt);
  75         else {
  76             //Check if we should do the snoop
  77             if (pkt->flags & SNOOP_COMMIT)
  78                 snoop(pkt);
  79         }
  80     }
  81     return true;
  82 }
  83
  84 template<class TagStore, class Buffering, class Coherence>
  85 Tick
  86 Cache<TagStore,Buffering,Coherence>::
  87 doAtomicAccess(PacketPtr pkt, bool isCpuSide)
  88 {
  89     if (isCpuSide)
  90     {
  91         probe(pkt, true, NULL);
  92         //TEMP ALWAYS SUCCES FOR NOW
  93         pkt->result = Packet::Success;
  94     }
  95     else
  96     {
  97         if (pkt->isResponse())
  98             handleResponse(pkt);
  99         else
 100             return snoopProbe(pkt);
 101     }
 102     //Fix this timing info
 103     return hitLatency;
 104 }
 105
 106 template<class TagStore, class Buffering, class Coherence>
 107 void
 108 Cache<TagStore,Buffering,Coherence>::
 109 doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
 110 {
 111     if (isCpuSide)
 112     {
 113         //TEMP USE CPU?THREAD 0 0
 114         pkt->req->setThreadContext(0,0);
 115
 116         probe(pkt, false, memSidePort);
 117         //TEMP ALWAYS SUCCESFUL FOR NOW
 118         pkt->result = Packet::Success;
 119     }
 120     else
 121     {
 122             probe(pkt, false, cpuSidePort);
 123     }
 124 }
 125
 126 template<class TagStore, class Buffering, class Coherence>
 127 void
 128 Cache<TagStore,Buffering,Coherence>::
 129 recvStatusChange(Port::Status status, bool isCpuSide)
 130 {
 131
 132 }
 133
 134
 135 template<class TagStore, class Buffering, class Coherence>
 136 Cache<TagStore,Buffering,Coherence>::
 137 Cache(const std::string &_name,
 138       Cache<TagStore,Buffering,Coherence>::Params &params)
 139     : BaseCache(_name, params.baseParams),
 140       prefetchAccess(params.prefetchAccess),
 141       tags(params.tags), missQueue(params.missQueue),
 142       coherence(params.coherence), prefetcher(params.prefetcher),
 143       hitLatency(params.hitLatency)
 144 {
 145     tags->setCache(this);
 146     tags->setPrefetcher(prefetcher);
 147     missQueue->setCache(this);
 148     missQueue->setPrefetcher(prefetcher);
 149     coherence->setCache(this);
 150     prefetcher->setCache(this);
 151     prefetcher->setTags(tags);
 152     prefetcher->setBuffer(missQueue);
 153     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 154     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 155 }
 156
 157 template<class TagStore, class Buffering, class Coherence>
 158 void
 159 Cache<TagStore,Buffering,Coherence>::regStats()
 160 {
 161     BaseCache::regStats();
 162     tags->regStats(name());
 163     missQueue->regStats(name());
 164     coherence->regStats(name());
 165     prefetcher->regStats(name());
 166 }
 167
 168 template<class TagStore, class Buffering, class Coherence>
 169 bool
 170 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 171 {
 172 //@todo Add back in MemDebug Calls
 173 //    MemDebug::cacheAccess(pkt);
 174     BlkType *blk = NULL;
 175     PacketList writebacks;
 176     int size = blkSize;
 177     int lat = hitLatency;
 178     if (prefetchAccess) {
 179         //We are determining prefetches on access stream, call prefetcher
 180         prefetcher->handleMiss(pkt, curTick);
 181     }
 182     if (!pkt->req->isUncacheable()) {
 183         blk = tags->handleAccess(pkt, lat, writebacks);
 184     } else {
 185         size = pkt->getSize();
 186     }
 187     // If this is a block size write/hint (WH64) allocate the block here
 188     // if the coherence protocol allows it.
 189     /** @todo make the fast write alloc (wh64) work with coherence. */
 190     /** @todo Do we want to do fast writes for writebacks as well? */
 191     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 192         (pkt->cmd == Packet::WriteReq
 193          || pkt->cmd == Packet::WriteInvalidateReq) ) {
 194         // not outstanding misses, can do this
 195         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 196         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 197             if (outstanding_miss) {
 198                 warn("WriteInv doing a fastallocate"
 199                      "with an outstanding miss to the same address\n");
 200             }
 201             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 202                                    writebacks);
 203             ++fastWrites;
 204         }
 205     }
 206     while (!writebacks.empty()) {
 207         missQueue->doWriteback(writebacks.front());
 208         writebacks.pop_front();
 209     }
 210
 211     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
 212             (blk) ? "hit" : "miss");
 213
 214     if (blk) {
 215         // Hit
 216         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 217         // clear dirty bit if write through
 218         if (pkt->needsResponse())
 219             respond(pkt, curTick+lat);
 220         if (pkt->cmd == Packet::Writeback) {
 221             //Signal that you can kill the pkt/req
 222             pkt->flags |= SATISFIED;
 223         }
 224         return true;
 225     }
 226
 227     // Miss
 228     if (!pkt->req->isUncacheable()) {
 229         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 230         /** @todo Move miss count code into BaseCache */
 231         if (missCount) {
 232             --missCount;
 233             if (missCount == 0)
 234                 exitSimLoop("A cache reached the maximum miss count");
 235         }
 236     }
 237
 238     if (pkt->flags & SATISFIED) {
 239         // happens when a store conditional fails because it missed
 240         // the cache completely
 241         if (pkt->needsResponse())
 242             respond(pkt, curTick+lat);
 243     } else {
 244         missQueue->handleMiss(pkt, size, curTick + hitLatency);
 245     }
 246
 247     if (pkt->cmd == Packet::Writeback) {
 248         //Need to clean up the packet on a writeback miss, but leave the request
 249         delete pkt;
 250     }
 251
 252     return true;
 253 }
 254
 255
 256 template<class TagStore, class Buffering, class Coherence>
 257 PacketPtr
 258 Cache<TagStore,Buffering,Coherence>::getPacket()
 259 {
 260     assert(missQueue->havePending());
 261     PacketPtr pkt = missQueue->getPacket();
 262     if (pkt) {
 263         if (!pkt->req->isUncacheable()) {
 264             if (pkt->cmd == Packet::HardPFReq)
 265                 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 266             BlkType *blk = tags->findBlock(pkt);
 267             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 268                                               (blk)? blk->status : 0);
 269             missQueue->setBusCmd(pkt, cmd);
 270         }
 271     }
 272
 273     assert(!doMasterRequest() || missQueue->havePending());
 274     assert(!pkt || pkt->time <= curTick);
 275     SIGNAL_NACK_HACK = false;
 276     return pkt;
 277 }
 278
 279 template<class TagStore, class Buffering, class Coherence>
 280 void
 281 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
 282                                                 bool success)
 283 {
 284     if (success && !(SIGNAL_NACK_HACK)) {
 285         //Remember if it was an upgrade because writeback MSHR's are removed
 286         //in Mark in Service
 287         bool upgrade = (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq);
 288
 289         missQueue->markInService(mshr->pkt, mshr);
 290
 291         //Temp Hack for UPGRADES
 292         if (upgrade) {
 293             assert(pkt);  //Upgrades need to be fixed
 294             pkt->flags &= ~CACHE_LINE_FILL;
 295             BlkType *blk = tags->findBlock(pkt);
 296             CacheBlk::State old_state = (blk) ? blk->status : 0;
 297             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 298             if (old_state != new_state)
 299                 DPRINTF(Cache, "Block for blk addr %x moving from state "
 300                         "%i to %i\n", pkt->getAddr(), old_state, new_state);
 301             //Set the state on the upgrade
 302             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 303             PacketList writebacks;
 304             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 305             assert(writebacks.empty());
 306             missQueue->handleResponse(pkt, curTick + hitLatency);
 307         }
 308     } else if (pkt && !pkt->req->isUncacheable()) {
 309         pkt->flags &= ~NACKED_LINE;
 310         SIGNAL_NACK_HACK = false;
 311         pkt->flags &= ~SATISFIED;
 312         pkt->flags &= ~SNOOP_COMMIT;
 313
 314 //Rmove copy from mshr
 315         delete mshr->pkt;
 316         mshr->pkt = pkt;
 317
 318         missQueue->restoreOrigCmd(pkt);
 319     }
 320 }
 321
 322 template<class TagStore, class Buffering, class Coherence>
 323 void
 324 Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
 325 {
 326     BlkType *blk = NULL;
 327     if (pkt->senderState) {
 328         //Delete temp copy in MSHR, restore it.
 329         delete ((MSHR*)pkt->senderState)->pkt;
 330         ((MSHR*)pkt->senderState)->pkt = pkt;
 331         if (pkt->result == Packet::Nacked) {
 332             //pkt->reinitFromRequest();
 333             warn("NACKs from devices not connected to the same bus "
 334                  "not implemented\n");
 335             return;
 336         }
 337         if (pkt->result == Packet::BadAddress) {
 338             //Make the response a Bad address and send it
 339         }
 340 //      MemDebug::cacheResponse(pkt);
 341         DPRINTF(Cache, "Handling reponse to %x\n", pkt->getAddr());
 342
 343         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 344             DPRINTF(Cache, "Block for addr %x being updated in Cache\n",
 345                     pkt->getAddr());
 346             blk = tags->findBlock(pkt);
 347             CacheBlk::State old_state = (blk) ? blk->status : 0;
 348             PacketList writebacks;
 349             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 350             if (old_state != new_state)
 351                 DPRINTF(Cache, "Block for blk addr %x moving from "
 352                         "state %i to %i\n",
 353                         pkt->getAddr(),
 354                         old_state, new_state);
 355             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 356                                    new_state, writebacks, pkt);
 357             while (!writebacks.empty()) {
 358                     missQueue->doWriteback(writebacks.front());
 359                     writebacks.pop_front();
 360             }
 361         }
 362         missQueue->handleResponse(pkt, curTick + hitLatency);
 363     }
 364 }
 365
 366 template<class TagStore, class Buffering, class Coherence>
 367 PacketPtr
 368 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 369 {
 370     return coherence->getPacket();
 371 }
 372
 373 template<class TagStore, class Buffering, class Coherence>
 374 void
 375 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
 376                                                          MSHR *cshr,
 377                                                          bool success)
 378 {
 379     coherence->sendResult(pkt, cshr, success);
 380 }
 381
 382
 383 template<class TagStore, class Buffering, class Coherence>
 384 void
 385 Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
 386 {
 387     if (pkt->req->isUncacheable()) {
 388         //Can't get a hit on an uncacheable address
 389         //Revisit this for multi level coherence
 390         return;
 391     }
 392
 393     //Send a timing (true) invalidate up if the protocol calls for it
 394     coherence->propogateInvalidate(pkt, true);
 395
 396     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 397     BlkType *blk = tags->findBlock(pkt);
 398     MSHR *mshr = missQueue->findMSHR(blk_addr);
 399     if (coherence->hasProtocol() || pkt->isInvalidate()) {
 400         //@todo Move this into handle bus req
 401         //If we find an mshr, and it is in service, we need to NACK or
 402         //invalidate
 403         if (mshr) {
 404             if (mshr->inService) {
 405                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 406                     && (pkt->cmd != Packet::InvalidateReq
 407                         && pkt->cmd != Packet::WriteInvalidateReq)) {
 408                     //If the outstanding request was an invalidate
 409                     //(upgrade,readex,..)  Then we need to ACK the request
 410                     //until we get the data Also NACK if the outstanding
 411                     //request is not a cachefill (writeback)
 412                     assert(!(pkt->flags & SATISFIED));
 413                     pkt->flags |= SATISFIED;
 414                     pkt->flags |= NACKED_LINE;
 415                     SIGNAL_NACK_HACK = true;
 416                     ///@todo NACK's from other levels
 417                     //warn("NACKs from devices not connected to the same bus "
 418                     //"not implemented\n");
 419                     //respondToSnoop(pkt, curTick + hitLatency);
 420                     return;
 421                 }
 422                 else {
 423                     //The supplier will be someone else, because we are
 424                     //waiting for the data.  This should cause this cache to
 425                     //be forced to go to the shared state, not the exclusive
 426                     //even though the shared line won't be asserted.  But for
 427                     //now we will just invlidate ourselves and allow the other
 428                     //cache to go into the exclusive state.  @todo Make it so
 429                     //a read to a pending read doesn't invalidate.  @todo Make
 430                     //it so that a read to a pending read can't be exclusive
 431                     //now.
 432
 433                     //Set the address so find match works
 434                     //panic("Don't have invalidates yet\n");
 435                     invalidatePkt->addrOverride(pkt->getAddr());
 436
 437                     //Append the invalidate on
 438                     missQueue->addTarget(mshr,invalidatePkt);
 439                     DPRINTF(Cache, "Appending Invalidate to addr: %x\n",
 440                             pkt->getAddr());
 441                     return;
 442                 }
 443             }
 444         }
 445         //We also need to check the writeback buffers and handle those
 446         std::vector<MSHR *> writebacks;
 447         if (missQueue->findWrites(blk_addr, writebacks)) {
 448             DPRINTF(Cache, "Snoop hit in writeback to addr: %x\n",
 449                     pkt->getAddr());
 450
 451             //Look through writebacks for any non-uncachable writes, use that
 452             for (int i=0; i<writebacks.size(); i++) {
 453                 mshr = writebacks[i];
 454
 455                 if (!mshr->pkt->req->isUncacheable()) {
 456                     if (pkt->isRead()) {
 457                         //Only Upgrades don't get here
 458                         //Supply the data
 459                         assert(!(pkt->flags & SATISFIED));
 460                         pkt->flags |= SATISFIED;
 461
 462                         //If we are in an exclusive protocol, make it ask again
 463                         //to get write permissions (upgrade), signal shared
 464                         pkt->flags |= SHARED_LINE;
 465
 466                         assert(pkt->isRead());
 467                         Addr offset = pkt->getAddr() & (blkSize - 1);
 468                         assert(offset < blkSize);
 469                         assert(pkt->getSize() <= blkSize);
 470                         assert(offset + pkt->getSize() <=blkSize);
 471                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 472
 473                         respondToSnoop(pkt, curTick + hitLatency);
 474                     }
 475
 476                     if (pkt->isInvalidate()) {
 477                         //This must be an upgrade or other cache will take
 478                         //ownership
 479                         missQueue->markInService(mshr->pkt, mshr);
 480                     }
 481                     return;
 482                 }
 483             }
 484         }
 485     }
 486     CacheBlk::State new_state;
 487     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 488
 489     if (blk && mshr && !mshr->inService && new_state == 0) {
 490             //There was a outstanding write to a shared block, not need ReadEx
 491             //not update, so change No Allocate param in MSHR
 492             mshr->pkt->flags &= ~NO_ALLOCATE;
 493     }
 494
 495     if (satisfy) {
 496         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 497                 "now supplying data, new state is %i\n",
 498                 pkt->cmdString(), blk_addr, new_state);
 499
 500         tags->handleSnoop(blk, new_state, pkt);
 501         respondToSnoop(pkt, curTick + hitLatency);
 502         return;
 503     }
 504     if (blk)
 505         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 506                 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
 507
 508     tags->handleSnoop(blk, new_state);
 509 }
 510
 511 template<class TagStore, class Buffering, class Coherence>
 512 void
 513 Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
 514 {
 515     //Need to handle the response, if NACKED
 516     if (pkt->flags & NACKED_LINE) {
 517         //Need to mark it as not in service, and retry for bus
 518         assert(0); //Yeah, we saw a NACK come through
 519
 520         //For now this should never get called, we return false when we see a
 521         //NACK instead, by doing this we allow the bus_blocked mechanism to
 522         //handle the retry For now it retrys in just 2 cycles, need to figure
 523         //out how to change that Eventually we will want to also have success
 524         //come in as a parameter Need to make sure that we handle the
 525         //functionality that happens on successufl return of the sendAddr
 526         //function
 527     }
 528 }
 529
 530 template<class TagStore, class Buffering, class Coherence>
 531 void
 532 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 533 {
 534     tags->invalidateBlk(addr);
 535 }
 536
 537
 538 /**
 539  * @todo Fix to not assume write allocate
 540  */
 541 template<class TagStore, class Buffering, class Coherence>
 542 Tick
 543 Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
 544                                            CachePort* otherSidePort)
 545 {
 546 //    MemDebug::cacheProbe(pkt);
 547     if (!pkt->req->isUncacheable()) {
 548         if (pkt->isInvalidate() && !pkt->isRead() && !pkt->isWrite()) {
 549             //Upgrade or Invalidate, satisfy it, don't forward
 550             DPRINTF(Cache, "%s %x ?\n", pkt->cmdString(), pkt->getAddr());
 551             pkt->flags |= SATISFIED;
 552             return 0;
 553         }
 554     }
 555
 556     if (!update && (otherSidePort == cpuSidePort)) {
 557         // Still need to change data in all locations.
 558         otherSidePort->checkAndSendFunctional(pkt);
 559         if (pkt->isRead() && pkt->result == Packet::Success)
 560             return 0;
 561     }
 562
 563     PacketList writebacks;
 564     int lat;
 565     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 566
 567     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(),
 568             pkt->getAddr(), (blk) ? "hit" : "miss");
 569
 570
 571     // Need to check for outstanding misses and writes
 572     Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 573
 574     // There can only be one matching outstanding miss.
 575     MSHR* mshr = missQueue->findMSHR(blk_addr);
 576
 577     // There can be many matching outstanding writes.
 578     std::vector<MSHR*> writes;
 579     missQueue->findWrites(blk_addr, writes);
 580
 581     if (!update) {
 582         bool notDone = !(pkt->flags & SATISFIED); //Hit in cache (was a block)
 583         // Check for data in MSHR and writebuffer.
 584         if (mshr) {
 585             MSHR::TargetList *targets = mshr->getTargetList();
 586             MSHR::TargetList::iterator i = targets->begin();
 587             MSHR::TargetList::iterator end = targets->end();
 588             for (; i != end && notDone; ++i) {
 589                 PacketPtr target = *i;
 590                 // If the target contains data, and it overlaps the
 591                 // probed request, need to update data
 592                 if (target->intersect(pkt)) {
 593                     DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a MSHR\n",
 594                             pkt->cmdString(), blk_addr);
 595                     notDone = fixPacket(pkt, target);
 596                 }
 597             }
 598         }
 599         for (int i = 0; i < writes.size() && notDone; ++i) {
 600             PacketPtr write = writes[i]->pkt;
 601             if (write->intersect(pkt)) {
 602                 DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a writeback\n",
 603                         pkt->cmdString(), blk_addr);
 604                 notDone = fixPacket(pkt, write);
 605             }
 606         }
 607         if (notDone && otherSidePort == memSidePort) {
 608             otherSidePort->checkAndSendFunctional(pkt);
 609             assert(pkt->result == Packet::Success);
 610         }
 611         return 0;
 612     } else if (!blk && !(pkt->flags & SATISFIED)) {
 613         // update the cache state and statistics
 614         if (mshr || !writes.empty()){
 615             // Can't handle it, return request unsatisfied.
 616             panic("Atomic access ran into outstanding MSHR's or WB's!");
 617         }
 618         if (!pkt->req->isUncacheable()) {
 619                 // Fetch the cache block to fill
 620             BlkType *blk = tags->findBlock(pkt);
 621             Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 622                                                             (blk)? blk->status : 0);
 623
 624             PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 625
 626             busPkt->allocate();
 627
 628             busPkt->time = curTick;
 629
 630             DPRINTF(Cache, "Sending a atomic %s for %x\n",
 631                     busPkt->cmdString(), busPkt->getAddr());
 632
 633             lat = memSidePort->sendAtomic(busPkt);
 634
 635             //Be sure to flip the response to a request for coherence
 636             if (busPkt->needsResponse()) {
 637                 busPkt->makeAtomicResponse();
 638             }
 639
 640 /*              if (!(busPkt->flags & SATISFIED)) {
 641 // blocked at a higher level, just return
 642 return 0;
 643 }
 644
 645 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 646
 647             CacheBlk::State old_state = (blk) ? blk->status : 0;
 648             CacheBlk::State new_state =
 649                 coherence->getNewState(busPkt, old_state);
 650             DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
 651                     busPkt->cmdString(), busPkt->getAddr(), old_state);
 652             if (old_state != new_state)
 653                 DPRINTF(Cache, "Block for blk addr %x moving from state "
 654                         "%i to %i\n", busPkt->getAddr(), old_state, new_state);
 655
 656             tags->handleFill(blk, busPkt, new_state, writebacks, pkt);
 657             //Free the packet
 658             delete busPkt;
 659
 660             // Handle writebacks if needed
 661             while (!writebacks.empty()){
 662                 PacketPtr wbPkt = writebacks.front();
 663                 memSidePort->sendAtomic(wbPkt);
 664                 writebacks.pop_front();
 665                 delete wbPkt;
 666             }
 667                 return lat + hitLatency;
 668         } else {
 669             return memSidePort->sendAtomic(pkt);
 670         }
 671     } else {
 672         if (blk) {
 673             // There was a cache hit.
 674             // Handle writebacks if needed
 675             while (!writebacks.empty()){
 676                 memSidePort->sendAtomic(writebacks.front());
 677                 writebacks.pop_front();
 678             }
 679
 680             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 681         }
 682
 683         return hitLatency;
 684     }
 685
 686     return 0;
 687 }
 688
 689 template<class TagStore, class Buffering, class Coherence>
 690 Tick
 691 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 692 {
 693     //Send a atomic (false) invalidate up if the protocol calls for it
 694     coherence->propogateInvalidate(pkt, false);
 695
 696     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 697     BlkType *blk = tags->findBlock(pkt);
 698     MSHR *mshr = missQueue->findMSHR(blk_addr);
 699     CacheBlk::State new_state = 0;
 700     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 701     if (satisfy) {
 702         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 703                 "now supplying data, new state is %i\n",
 704                 pkt->cmdString(), blk_addr, new_state);
 705
 706             tags->handleSnoop(blk, new_state, pkt);
 707             return hitLatency;
 708     }
 709     if (blk)
 710         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 711                 "new state is %i\n",
 712                     pkt->cmdString(), blk_addr, new_state);
 713     tags->handleSnoop(blk, new_state);
 714     return 0;
 715 }
 716