src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         probe(pkt, true, NULL);
  90         //TEMP ALWAYS SUCCES FOR NOW
  91         pkt->result = Packet::Success;
  92     }
  93     else
  94     {
  95         if (pkt->isResponse())
  96             handleResponse(pkt);
  97         else
  98             return snoopProbe(pkt);
  99     }
 100     //Fix this timing info
 101     return hitLatency;
 102 }
 103
 104 template<class TagStore, class Buffering, class Coherence>
 105 void
 106 Cache<TagStore,Buffering,Coherence>::
 107 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 108 {
 109     if (isCpuSide)
 110     {
 111         //TEMP USE CPU?THREAD 0 0
 112         pkt->req->setThreadContext(0,0);
 113
 114         probe(pkt, false, memSidePort);
 115         //TEMP ALWAYS SUCCESFUL FOR NOW
 116         pkt->result = Packet::Success;
 117     }
 118     else
 119     {
 120             probe(pkt, false, cpuSidePort);
 121     }
 122 }
 123
 124 template<class TagStore, class Buffering, class Coherence>
 125 void
 126 Cache<TagStore,Buffering,Coherence>::
 127 recvStatusChange(Port::Status status, bool isCpuSide)
 128 {
 129
 130 }
 131
 132
 133 template<class TagStore, class Buffering, class Coherence>
 134 Cache<TagStore,Buffering,Coherence>::
 135 Cache(const std::string &_name,
 136       Cache<TagStore,Buffering,Coherence>::Params &params)
 137     : BaseCache(_name, params.baseParams),
 138       prefetchAccess(params.prefetchAccess),
 139       tags(params.tags), missQueue(params.missQueue),
 140       coherence(params.coherence), prefetcher(params.prefetcher),
 141       hitLatency(params.hitLatency)
 142 {
 143     tags->setCache(this);
 144     tags->setPrefetcher(prefetcher);
 145     missQueue->setCache(this);
 146     missQueue->setPrefetcher(prefetcher);
 147     coherence->setCache(this);
 148     prefetcher->setCache(this);
 149     prefetcher->setTags(tags);
 150     prefetcher->setBuffer(missQueue);
 151     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 152     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 153 }
 154
 155 template<class TagStore, class Buffering, class Coherence>
 156 void
 157 Cache<TagStore,Buffering,Coherence>::regStats()
 158 {
 159     BaseCache::regStats();
 160     tags->regStats(name());
 161     missQueue->regStats(name());
 162     coherence->regStats(name());
 163     prefetcher->regStats(name());
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 bool
 168 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 169 {
 170 //@todo Add back in MemDebug Calls
 171 //    MemDebug::cacheAccess(pkt);
 172     BlkType *blk = NULL;
 173     PacketList writebacks;
 174     int size = blkSize;
 175     int lat = hitLatency;
 176     if (prefetchAccess) {
 177         //We are determining prefetches on access stream, call prefetcher
 178         prefetcher->handleMiss(pkt, curTick);
 179     }
 180     if (!pkt->req->isUncacheable()) {
 181         blk = tags->handleAccess(pkt, lat, writebacks);
 182     } else {
 183         size = pkt->getSize();
 184     }
 185     // If this is a block size write/hint (WH64) allocate the block here
 186     // if the coherence protocol allows it.
 187     /** @todo make the fast write alloc (wh64) work with coherence. */
 188     /** @todo Do we want to do fast writes for writebacks as well? */
 189     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 190         (pkt->cmd == Packet::WriteReq
 191          || pkt->cmd == Packet::WriteInvalidateReq) ) {
 192         // not outstanding misses, can do this
 193         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 194         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 195             if (outstanding_miss) {
 196                 warn("WriteInv doing a fastallocate"
 197                      "with an outstanding miss to the same address\n");
 198             }
 199             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 200                                    writebacks);
 201             ++fastWrites;
 202         }
 203     }
 204     while (!writebacks.empty()) {
 205         missQueue->doWriteback(writebacks.front());
 206         writebacks.pop_front();
 207     }
 208     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 209             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 210             pkt->getAddr() & ~((Addr)blkSize - 1));
 211     if (blk) {
 212         // Hit
 213         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 214         // clear dirty bit if write through
 215         if (pkt->needsResponse())
 216             respond(pkt, curTick+lat);
 217         if (pkt->cmd == Packet::Writeback) {
 218             //Signal that you can kill the pkt/req
 219             pkt->flags |= SATISFIED;
 220         }
 221         return true;
 222     }
 223
 224     // Miss
 225     if (!pkt->req->isUncacheable()) {
 226         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 227         /** @todo Move miss count code into BaseCache */
 228         if (missCount) {
 229             --missCount;
 230             if (missCount == 0)
 231                 exitSimLoop("A cache reached the maximum miss count");
 232         }
 233     }
 234     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 235 //    return MA_CACHE_MISS;
 236     return true;
 237 }
 238
 239
 240 template<class TagStore, class Buffering, class Coherence>
 241 Packet *
 242 Cache<TagStore,Buffering,Coherence>::getPacket()
 243 {
 244     assert(missQueue->havePending());
 245     Packet * pkt = missQueue->getPacket();
 246     if (pkt) {
 247         if (!pkt->req->isUncacheable()) {
 248             if (pkt->cmd == Packet::HardPFReq)
 249                 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 250             BlkType *blk = tags->findBlock(pkt);
 251             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 252                                               (blk)? blk->status : 0);
 253             missQueue->setBusCmd(pkt, cmd);
 254         }
 255     }
 256
 257     assert(!doMasterRequest() || missQueue->havePending());
 258     assert(!pkt || pkt->time <= curTick);
 259     return pkt;
 260 }
 261
 262 template<class TagStore, class Buffering, class Coherence>
 263 void
 264 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
 265                                                 bool success)
 266 {
 267     if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
 268         if (!mshr->pkt->needsResponse()
 269             && !(mshr->pkt->cmd == Packet::UpgradeReq)
 270             && (pkt && (pkt->flags & SATISFIED))) {
 271             //Writeback, clean up the non copy version of the packet
 272             delete pkt;
 273         }
 274         missQueue->markInService(mshr->pkt, mshr);
 275         //Temp Hack for UPGRADES
 276         if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
 277             assert(pkt);  //Upgrades need to be fixed
 278             pkt->flags &= ~CACHE_LINE_FILL;
 279             BlkType *blk = tags->findBlock(pkt);
 280             CacheBlk::State old_state = (blk) ? blk->status : 0;
 281             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 282             if (old_state != new_state)
 283                 DPRINTF(Cache, "Block for blk addr %x moving from "
 284                         "state %i to %i\n",
 285                         pkt->getAddr() & (((ULL(1))<<48)-1),
 286                         old_state, new_state);
 287             //Set the state on the upgrade
 288             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 289             PacketList writebacks;
 290             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 291             assert(writebacks.empty());
 292             missQueue->handleResponse(pkt, curTick + hitLatency);
 293         }
 294     } else if (pkt && !pkt->req->isUncacheable()) {
 295         pkt->flags &= ~NACKED_LINE;
 296         pkt->flags &= ~SATISFIED;
 297         pkt->flags &= ~SNOOP_COMMIT;
 298
 299 //Rmove copy from mshr
 300         delete mshr->pkt;
 301         mshr->pkt = pkt;
 302
 303         missQueue->restoreOrigCmd(pkt);
 304     }
 305 }
 306
 307 template<class TagStore, class Buffering, class Coherence>
 308 void
 309 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 310 {
 311     BlkType *blk = NULL;
 312     if (pkt->senderState) {
 313         //Delete temp copy in MSHR, restore it.
 314         delete ((MSHR*)pkt->senderState)->pkt;
 315         ((MSHR*)pkt->senderState)->pkt = pkt;
 316         if (pkt->result == Packet::Nacked) {
 317             //pkt->reinitFromRequest();
 318             warn("NACKs from devices not connected to the same bus "
 319                  "not implemented\n");
 320             return;
 321         }
 322         if (pkt->result == Packet::BadAddress) {
 323             //Make the response a Bad address and send it
 324         }
 325 //      MemDebug::cacheResponse(pkt);
 326         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 327                 pkt->getAddr() & (((ULL(1))<<48)-1));
 328
 329         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 330             blk = tags->findBlock(pkt);
 331             CacheBlk::State old_state = (blk) ? blk->status : 0;
 332             PacketList writebacks;
 333             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 334             if (old_state != new_state)
 335                 DPRINTF(Cache, "Block for blk addr %x moving from "
 336                         "state %i to %i\n",
 337                         pkt->getAddr() & (((ULL(1))<<48)-1),
 338                         old_state, new_state);
 339             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 340                                    new_state, writebacks, pkt);
 341             while (!writebacks.empty()) {
 342                     missQueue->doWriteback(writebacks.front());
 343                     writebacks.pop_front();
 344             }
 345         }
 346         missQueue->handleResponse(pkt, curTick + hitLatency);
 347     }
 348 }
 349
 350 template<class TagStore, class Buffering, class Coherence>
 351 Packet *
 352 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 353 {
 354     return coherence->getPacket();
 355 }
 356
 357 template<class TagStore, class Buffering, class Coherence>
 358 void
 359 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
 360                                                          MSHR *cshr,
 361                                                          bool success)
 362 {
 363     coherence->sendResult(pkt, cshr, success);
 364 }
 365
 366
 367 template<class TagStore, class Buffering, class Coherence>
 368 void
 369 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 370 {
 371     if (pkt->req->isUncacheable()) {
 372         //Can't get a hit on an uncacheable address
 373         //Revisit this for multi level coherence
 374         return;
 375     }
 376
 377     //Send a timing (true) invalidate up if the protocol calls for it
 378     coherence->propogateInvalidate(pkt, true);
 379
 380     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 381     BlkType *blk = tags->findBlock(pkt);
 382     MSHR *mshr = missQueue->findMSHR(blk_addr);
 383     if (coherence->hasProtocol() || pkt->isInvalidate()) {
 384         //@todo Move this into handle bus req
 385         //If we find an mshr, and it is in service, we need to NACK or
 386         //invalidate
 387         if (mshr) {
 388             if (mshr->inService) {
 389                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 390                     && (pkt->cmd != Packet::InvalidateReq
 391                         && pkt->cmd != Packet::WriteInvalidateReq)) {
 392                     //If the outstanding request was an invalidate
 393                     //(upgrade,readex,..)  Then we need to ACK the request
 394                     //until we get the data Also NACK if the outstanding
 395                     //request is not a cachefill (writeback)
 396                     assert(!(pkt->flags & SATISFIED));
 397                     pkt->flags |= SATISFIED;
 398                     pkt->flags |= NACKED_LINE;
 399                     ///@todo NACK's from other levels
 400                     //warn("NACKs from devices not connected to the same bus "
 401                     //"not implemented\n");
 402                     //respondToSnoop(pkt, curTick + hitLatency);
 403                     return;
 404                 }
 405                 else {
 406                     //The supplier will be someone else, because we are
 407                     //waiting for the data.  This should cause this cache to
 408                     //be forced to go to the shared state, not the exclusive
 409                     //even though the shared line won't be asserted.  But for
 410                     //now we will just invlidate ourselves and allow the other
 411                     //cache to go into the exclusive state.  @todo Make it so
 412                     //a read to a pending read doesn't invalidate.  @todo Make
 413                     //it so that a read to a pending read can't be exclusive
 414                     //now.
 415
 416                     //Set the address so find match works
 417                     //panic("Don't have invalidates yet\n");
 418                     invalidatePkt->addrOverride(pkt->getAddr());
 419
 420                     //Append the invalidate on
 421                     missQueue->addTarget(mshr,invalidatePkt);
 422                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n",
 423                             pkt->getAddr() & (((ULL(1))<<48)-1));
 424                     return;
 425                 }
 426             }
 427         }
 428         //We also need to check the writeback buffers and handle those
 429         std::vector<MSHR *> writebacks;
 430         if (missQueue->findWrites(blk_addr, writebacks)) {
 431             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n",
 432                     pkt->getAddr() & (((ULL(1))<<48)-1));
 433
 434             //Look through writebacks for any non-uncachable writes, use that
 435             for (int i=0; i<writebacks.size(); i++) {
 436                 mshr = writebacks[i];
 437
 438                 if (!mshr->pkt->req->isUncacheable()) {
 439                     if (pkt->isRead()) {
 440                         //Only Upgrades don't get here
 441                         //Supply the data
 442                         assert(!(pkt->flags & SATISFIED));
 443                         pkt->flags |= SATISFIED;
 444
 445                         //If we are in an exclusive protocol, make it ask again
 446                         //to get write permissions (upgrade), signal shared
 447                         pkt->flags |= SHARED_LINE;
 448
 449                         assert(pkt->isRead());
 450                         Addr offset = pkt->getAddr() & (blkSize - 1);
 451                         assert(offset < blkSize);
 452                         assert(pkt->getSize() <= blkSize);
 453                         assert(offset + pkt->getSize() <=blkSize);
 454                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 455
 456                         respondToSnoop(pkt, curTick + hitLatency);
 457                     }
 458
 459                     if (pkt->isInvalidate()) {
 460                         //This must be an upgrade or other cache will take
 461                         //ownership
 462                         missQueue->markInService(mshr->pkt, mshr);
 463                     }
 464                     return;
 465                 }
 466             }
 467         }
 468     }
 469     CacheBlk::State new_state;
 470     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 471     if (satisfy) {
 472         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 473                 "now supplying data, new state is %i\n",
 474                 pkt->cmdString(), blk_addr, new_state);
 475
 476         tags->handleSnoop(blk, new_state, pkt);
 477         respondToSnoop(pkt, curTick + hitLatency);
 478         return;
 479     }
 480     if (blk)
 481         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 482                 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
 483     tags->handleSnoop(blk, new_state);
 484 }
 485
 486 template<class TagStore, class Buffering, class Coherence>
 487 void
 488 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 489 {
 490     //Need to handle the response, if NACKED
 491     if (pkt->flags & NACKED_LINE) {
 492         //Need to mark it as not in service, and retry for bus
 493         assert(0); //Yeah, we saw a NACK come through
 494
 495         //For now this should never get called, we return false when we see a
 496         //NACK instead, by doing this we allow the bus_blocked mechanism to
 497         //handle the retry For now it retrys in just 2 cycles, need to figure
 498         //out how to change that Eventually we will want to also have success
 499         //come in as a parameter Need to make sure that we handle the
 500         //functionality that happens on successufl return of the sendAddr
 501         //function
 502     }
 503 }
 504
 505 template<class TagStore, class Buffering, class Coherence>
 506 void
 507 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 508 {
 509     tags->invalidateBlk(addr);
 510 }
 511
 512
 513 /**
 514  * @todo Fix to not assume write allocate
 515  */
 516 template<class TagStore, class Buffering, class Coherence>
 517 Tick
 518 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
 519                                            CachePort* otherSidePort)
 520 {
 521 //    MemDebug::cacheProbe(pkt);
 522     if (!pkt->req->isUncacheable()) {
 523         if (pkt->isInvalidate() && !pkt->isRead()
 524             && !pkt->isWrite()) {
 525             //Upgrade or Invalidate, satisfy it, don't forward
 526             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 527                     pkt->getAddr() & (((ULL(1))<<48)-1),
 528                     pkt->getAddr() & ~((Addr)blkSize - 1));
 529             pkt->flags |= SATISFIED;
 530             return 0;
 531         }
 532     }
 533
 534     if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
 535         // Still need to change data in all locations.
 536         otherSidePort->sendFunctional(pkt);
 537         if (pkt->isRead() && pkt->result == Packet::Success)
 538             return 0;
 539     }
 540
 541     PacketList writebacks;
 542     int lat;
 543     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 544
 545     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 546             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 547             pkt->getAddr() & ~((Addr)blkSize - 1));
 548
 549
 550     // Need to check for outstanding misses and writes
 551     Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 552
 553     // There can only be one matching outstanding miss.
 554     MSHR* mshr = missQueue->findMSHR(blk_addr);
 555
 556     // There can be many matching outstanding writes.
 557     std::vector<MSHR*> writes;
 558     missQueue->findWrites(blk_addr, writes);
 559
 560     if (!update) {
 561         // Check for data in MSHR and writebuffer.
 562         if (mshr) {
 563             warn("Found outstanding miss on an non-update probe");
 564             MSHR::TargetList *targets = mshr->getTargetList();
 565             MSHR::TargetList::iterator i = targets->begin();
 566             MSHR::TargetList::iterator end = targets->end();
 567             for (; i != end; ++i) {
 568                 Packet * target = *i;
 569                 // If the target contains data, and it overlaps the
 570                 // probed request, need to update data
 571                 if (target->isWrite() && target->intersect(pkt)) {
 572                     uint8_t* pkt_data;
 573                     uint8_t* write_data;
 574                     int data_size;
 575                     if (target->getAddr() < pkt->getAddr()) {
 576                         int offset = pkt->getAddr() - target->getAddr();
 577                         pkt_data = pkt->getPtr<uint8_t>();
 578                         write_data = target->getPtr<uint8_t>() + offset;
 579                         data_size = target->getSize() - offset;
 580                         assert(data_size > 0);
 581                         if (data_size > pkt->getSize())
 582                             data_size = pkt->getSize();
 583                     } else {
 584                         int offset = target->getAddr() - pkt->getAddr();
 585                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 586                         write_data = target->getPtr<uint8_t>();
 587                         data_size = pkt->getSize() - offset;
 588                         assert(data_size >= pkt->getSize());
 589                         if (data_size > target->getSize())
 590                             data_size = target->getSize();
 591                     }
 592
 593                     if (pkt->isWrite()) {
 594                         memcpy(pkt_data, write_data, data_size);
 595                     } else {
 596                         pkt->flags |= SATISFIED;
 597                         pkt->result = Packet::Success;
 598                         memcpy(write_data, pkt_data, data_size);
 599                     }
 600                 }
 601             }
 602         }
 603         for (int i = 0; i < writes.size(); ++i) {
 604             Packet * write = writes[i]->pkt;
 605             if (write->intersect(pkt)) {
 606                 warn("Found outstanding write on an non-update probe");
 607                 uint8_t* pkt_data;
 608                 uint8_t* write_data;
 609                 int data_size;
 610                 if (write->getAddr() < pkt->getAddr()) {
 611                     int offset = pkt->getAddr() - write->getAddr();
 612                     pkt_data = pkt->getPtr<uint8_t>();
 613                     write_data = write->getPtr<uint8_t>() + offset;
 614                     data_size = write->getSize() - offset;
 615                     assert(data_size > 0);
 616                     if (data_size > pkt->getSize())
 617                         data_size = pkt->getSize();
 618                 } else {
 619                     int offset = write->getAddr() - pkt->getAddr();
 620                     pkt_data = pkt->getPtr<uint8_t>() + offset;
 621                     write_data = write->getPtr<uint8_t>();
 622                     data_size = pkt->getSize() - offset;
 623                     assert(data_size >= pkt->getSize());
 624                     if (data_size > write->getSize())
 625                         data_size = write->getSize();
 626                 }
 627
 628                 if (pkt->isWrite()) {
 629                     memcpy(pkt_data, write_data, data_size);
 630                 } else {
 631                     pkt->flags |= SATISFIED;
 632                     pkt->result = Packet::Success;
 633                     memcpy(write_data, pkt_data, data_size);
 634                 }
 635
 636             }
 637         }
 638         if (pkt->isRead()
 639             && pkt->result != Packet::Success
 640             && otherSidePort == memSidePort) {
 641             otherSidePort->sendFunctional(pkt);
 642             assert(pkt->result == Packet::Success);
 643         }
 644         return 0;
 645     } else if (!blk) {
 646         // update the cache state and statistics
 647         if (mshr || !writes.empty()){
 648             // Can't handle it, return pktuest unsatisfied.
 649             panic("Atomic access ran into outstanding MSHR's or WB's!");
 650         }
 651         if (!pkt->req->isUncacheable()) {
 652                 // Fetch the cache block to fill
 653             BlkType *blk = tags->findBlock(pkt);
 654             Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 655                                                             (blk)? blk->status : 0);
 656
 657             Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 658
 659             busPkt->allocate();
 660
 661             busPkt->time = curTick;
 662
 663             DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 664                     busPkt->cmdString(),
 665                     busPkt->getAddr() & (((ULL(1))<<48)-1),
 666                     busPkt->getAddr() & ~((Addr)blkSize - 1));
 667
 668             lat = memSidePort->sendAtomic(busPkt);
 669
 670             //Be sure to flip the response to a request for coherence
 671             if (busPkt->needsResponse()) {
 672                 busPkt->makeAtomicResponse();
 673             }
 674
 675 /*              if (!(busPkt->flags & SATISFIED)) {
 676 // blocked at a higher level, just return
 677 return 0;
 678 }
 679
 680 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 681
 682             CacheBlk::State old_state = (blk) ? blk->status : 0;
 683             CacheBlk::State new_state =
 684                 coherence->getNewState(busPkt, old_state);
 685             DPRINTF(Cache,
 686                         "Receive response:%s for blk addr %x in state %i\n",
 687                     busPkt->cmdString(),
 688                     busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 689             if (old_state != new_state)
 690                     DPRINTF(Cache, "Block for blk addr %x moving from "
 691                             "state %i to %i\n",
 692                             busPkt->getAddr() & (((ULL(1))<<48)-1),
 693                             old_state, new_state);
 694
 695             tags->handleFill(blk, busPkt,
 696                              new_state,
 697                              writebacks, pkt);
 698             //Free the packet
 699             delete busPkt;
 700
 701             // Handle writebacks if needed
 702             while (!writebacks.empty()){
 703                 Packet *wbPkt = writebacks.front();
 704                 memSidePort->sendAtomic(wbPkt);
 705                 writebacks.pop_front();
 706                 delete wbPkt;
 707             }
 708                 return lat + hitLatency;
 709         } else {
 710             return memSidePort->sendAtomic(pkt);
 711         }
 712     } else {
 713         // There was a cache hit.
 714         // Handle writebacks if needed
 715         while (!writebacks.empty()){
 716             memSidePort->sendAtomic(writebacks.front());
 717             writebacks.pop_front();
 718         }
 719
 720         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 721
 722         return hitLatency;
 723     }
 724     fatal("Probe not handled.\n");
 725     return 0;
 726 }
 727
 728 template<class TagStore, class Buffering, class Coherence>
 729 Tick
 730 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 731 {
 732     //Send a atomic (false) invalidate up if the protocol calls for it
 733     coherence->propogateInvalidate(pkt, false);
 734
 735     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 736     BlkType *blk = tags->findBlock(pkt);
 737     MSHR *mshr = missQueue->findMSHR(blk_addr);
 738     CacheBlk::State new_state = 0;
 739     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 740     if (satisfy) {
 741         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 742                 "now supplying data, new state is %i\n",
 743                 pkt->cmdString(), blk_addr, new_state);
 744
 745             tags->handleSnoop(blk, new_state, pkt);
 746             return hitLatency;
 747     }
 748     if (blk)
 749         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 750                 "new state is %i\n",
 751                     pkt->cmdString(), blk_addr, new_state);
 752     tags->handleSnoop(blk, new_state);
 753     return 0;
 754 }
 755