src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(PacketPtr pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         probe(pkt, true, NULL);
  90         //TEMP ALWAYS SUCCES FOR NOW
  91         pkt->result = Packet::Success;
  92     }
  93     else
  94     {
  95         if (pkt->isResponse())
  96             handleResponse(pkt);
  97         else
  98             return snoopProbe(pkt);
  99     }
 100     //Fix this timing info
 101     return hitLatency;
 102 }
 103
 104 template<class TagStore, class Buffering, class Coherence>
 105 void
 106 Cache<TagStore,Buffering,Coherence>::
 107 doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
 108 {
 109     if (isCpuSide)
 110     {
 111         //TEMP USE CPU?THREAD 0 0
 112         pkt->req->setThreadContext(0,0);
 113
 114         probe(pkt, false, memSidePort);
 115         //TEMP ALWAYS SUCCESFUL FOR NOW
 116         pkt->result = Packet::Success;
 117     }
 118     else
 119     {
 120             probe(pkt, false, cpuSidePort);
 121     }
 122 }
 123
 124 template<class TagStore, class Buffering, class Coherence>
 125 void
 126 Cache<TagStore,Buffering,Coherence>::
 127 recvStatusChange(Port::Status status, bool isCpuSide)
 128 {
 129
 130 }
 131
 132
 133 template<class TagStore, class Buffering, class Coherence>
 134 Cache<TagStore,Buffering,Coherence>::
 135 Cache(const std::string &_name,
 136       Cache<TagStore,Buffering,Coherence>::Params &params)
 137     : BaseCache(_name, params.baseParams),
 138       prefetchAccess(params.prefetchAccess),
 139       tags(params.tags), missQueue(params.missQueue),
 140       coherence(params.coherence), prefetcher(params.prefetcher),
 141       hitLatency(params.hitLatency)
 142 {
 143     tags->setCache(this);
 144     tags->setPrefetcher(prefetcher);
 145     missQueue->setCache(this);
 146     missQueue->setPrefetcher(prefetcher);
 147     coherence->setCache(this);
 148     prefetcher->setCache(this);
 149     prefetcher->setTags(tags);
 150     prefetcher->setBuffer(missQueue);
 151     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 152     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 153 }
 154
 155 template<class TagStore, class Buffering, class Coherence>
 156 void
 157 Cache<TagStore,Buffering,Coherence>::regStats()
 158 {
 159     BaseCache::regStats();
 160     tags->regStats(name());
 161     missQueue->regStats(name());
 162     coherence->regStats(name());
 163     prefetcher->regStats(name());
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 bool
 168 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 169 {
 170 //@todo Add back in MemDebug Calls
 171 //    MemDebug::cacheAccess(pkt);
 172     BlkType *blk = NULL;
 173     PacketList writebacks;
 174     int size = blkSize;
 175     int lat = hitLatency;
 176     if (prefetchAccess) {
 177         //We are determining prefetches on access stream, call prefetcher
 178         prefetcher->handleMiss(pkt, curTick);
 179     }
 180     if (!pkt->req->isUncacheable()) {
 181         blk = tags->handleAccess(pkt, lat, writebacks);
 182     } else {
 183         size = pkt->getSize();
 184     }
 185     // If this is a block size write/hint (WH64) allocate the block here
 186     // if the coherence protocol allows it.
 187     /** @todo make the fast write alloc (wh64) work with coherence. */
 188     /** @todo Do we want to do fast writes for writebacks as well? */
 189     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 190         (pkt->cmd == Packet::WriteReq
 191          || pkt->cmd == Packet::WriteInvalidateReq) ) {
 192         // not outstanding misses, can do this
 193         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 194         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 195             if (outstanding_miss) {
 196                 warn("WriteInv doing a fastallocate"
 197                      "with an outstanding miss to the same address\n");
 198             }
 199             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 200                                    writebacks);
 201             ++fastWrites;
 202         }
 203     }
 204     while (!writebacks.empty()) {
 205         missQueue->doWriteback(writebacks.front());
 206         writebacks.pop_front();
 207     }
 208
 209     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
 210             (blk) ? "hit" : "miss");
 211
 212     if (blk) {
 213         // Hit
 214         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 215         // clear dirty bit if write through
 216         if (pkt->needsResponse())
 217             respond(pkt, curTick+lat);
 218         if (pkt->cmd == Packet::Writeback) {
 219             //Signal that you can kill the pkt/req
 220             pkt->flags |= SATISFIED;
 221         }
 222         return true;
 223     }
 224
 225     // Miss
 226     if (!pkt->req->isUncacheable()) {
 227         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 228         /** @todo Move miss count code into BaseCache */
 229         if (missCount) {
 230             --missCount;
 231             if (missCount == 0)
 232                 exitSimLoop("A cache reached the maximum miss count");
 233         }
 234     }
 235
 236     if (pkt->flags & SATISFIED) {
 237         // happens when a store conditional fails because it missed
 238         // the cache completely
 239         if (pkt->needsResponse())
 240             respond(pkt, curTick+lat);
 241     } else {
 242         missQueue->handleMiss(pkt, size, curTick + hitLatency);
 243     }
 244
 245     return true;
 246 }
 247
 248
 249 template<class TagStore, class Buffering, class Coherence>
 250 PacketPtr
 251 Cache<TagStore,Buffering,Coherence>::getPacket()
 252 {
 253     assert(missQueue->havePending());
 254     PacketPtr pkt = missQueue->getPacket();
 255     if (pkt) {
 256         if (!pkt->req->isUncacheable()) {
 257             if (pkt->cmd == Packet::HardPFReq)
 258                 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 259             BlkType *blk = tags->findBlock(pkt);
 260             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 261                                               (blk)? blk->status : 0);
 262             missQueue->setBusCmd(pkt, cmd);
 263         }
 264     }
 265
 266     assert(!doMasterRequest() || missQueue->havePending());
 267     assert(!pkt || pkt->time <= curTick);
 268     return pkt;
 269 }
 270
 271 template<class TagStore, class Buffering, class Coherence>
 272 void
 273 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
 274                                                 bool success)
 275 {
 276     if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
 277         if (!mshr->pkt->needsResponse()
 278             && !(mshr->pkt->cmd == Packet::UpgradeReq)
 279             && (pkt && (pkt->flags & SATISFIED))) {
 280             //Writeback, clean up the non copy version of the packet
 281             delete pkt;
 282         }
 283         missQueue->markInService(mshr->pkt, mshr);
 284         //Temp Hack for UPGRADES
 285         if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
 286             assert(pkt);  //Upgrades need to be fixed
 287             pkt->flags &= ~CACHE_LINE_FILL;
 288             BlkType *blk = tags->findBlock(pkt);
 289             CacheBlk::State old_state = (blk) ? blk->status : 0;
 290             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 291             if (old_state != new_state)
 292                 DPRINTF(Cache, "Block for blk addr %x moving from state "
 293                         "%i to %i\n", pkt->getAddr(), old_state, new_state);
 294             //Set the state on the upgrade
 295             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 296             PacketList writebacks;
 297             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 298             assert(writebacks.empty());
 299             missQueue->handleResponse(pkt, curTick + hitLatency);
 300         }
 301     } else if (pkt && !pkt->req->isUncacheable()) {
 302         pkt->flags &= ~NACKED_LINE;
 303         pkt->flags &= ~SATISFIED;
 304         pkt->flags &= ~SNOOP_COMMIT;
 305
 306 //Rmove copy from mshr
 307         delete mshr->pkt;
 308         mshr->pkt = pkt;
 309
 310         missQueue->restoreOrigCmd(pkt);
 311     }
 312 }
 313
 314 template<class TagStore, class Buffering, class Coherence>
 315 void
 316 Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
 317 {
 318     BlkType *blk = NULL;
 319     if (pkt->senderState) {
 320         //Delete temp copy in MSHR, restore it.
 321         delete ((MSHR*)pkt->senderState)->pkt;
 322         ((MSHR*)pkt->senderState)->pkt = pkt;
 323         if (pkt->result == Packet::Nacked) {
 324             //pkt->reinitFromRequest();
 325             warn("NACKs from devices not connected to the same bus "
 326                  "not implemented\n");
 327             return;
 328         }
 329         if (pkt->result == Packet::BadAddress) {
 330             //Make the response a Bad address and send it
 331         }
 332 //      MemDebug::cacheResponse(pkt);
 333         DPRINTF(Cache, "Handling reponse to %x\n", pkt->getAddr());
 334
 335         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 336             blk = tags->findBlock(pkt);
 337             CacheBlk::State old_state = (blk) ? blk->status : 0;
 338             PacketList writebacks;
 339             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 340             if (old_state != new_state)
 341                 DPRINTF(Cache, "Block for blk addr %x moving from "
 342                         "state %i to %i\n",
 343                         pkt->getAddr(),
 344                         old_state, new_state);
 345             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 346                                    new_state, writebacks, pkt);
 347             while (!writebacks.empty()) {
 348                     missQueue->doWriteback(writebacks.front());
 349                     writebacks.pop_front();
 350             }
 351         }
 352         missQueue->handleResponse(pkt, curTick + hitLatency);
 353     }
 354 }
 355
 356 template<class TagStore, class Buffering, class Coherence>
 357 PacketPtr
 358 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 359 {
 360     return coherence->getPacket();
 361 }
 362
 363 template<class TagStore, class Buffering, class Coherence>
 364 void
 365 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
 366                                                          MSHR *cshr,
 367                                                          bool success)
 368 {
 369     coherence->sendResult(pkt, cshr, success);
 370 }
 371
 372
 373 template<class TagStore, class Buffering, class Coherence>
 374 void
 375 Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
 376 {
 377     if (pkt->req->isUncacheable()) {
 378         //Can't get a hit on an uncacheable address
 379         //Revisit this for multi level coherence
 380         return;
 381     }
 382
 383     //Send a timing (true) invalidate up if the protocol calls for it
 384     coherence->propogateInvalidate(pkt, true);
 385
 386     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 387     BlkType *blk = tags->findBlock(pkt);
 388     MSHR *mshr = missQueue->findMSHR(blk_addr);
 389     if (coherence->hasProtocol() || pkt->isInvalidate()) {
 390         //@todo Move this into handle bus req
 391         //If we find an mshr, and it is in service, we need to NACK or
 392         //invalidate
 393         if (mshr) {
 394             if (mshr->inService) {
 395                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 396                     && (pkt->cmd != Packet::InvalidateReq
 397                         && pkt->cmd != Packet::WriteInvalidateReq)) {
 398                     //If the outstanding request was an invalidate
 399                     //(upgrade,readex,..)  Then we need to ACK the request
 400                     //until we get the data Also NACK if the outstanding
 401                     //request is not a cachefill (writeback)
 402                     assert(!(pkt->flags & SATISFIED));
 403                     pkt->flags |= SATISFIED;
 404                     pkt->flags |= NACKED_LINE;
 405                     ///@todo NACK's from other levels
 406                     //warn("NACKs from devices not connected to the same bus "
 407                     //"not implemented\n");
 408                     //respondToSnoop(pkt, curTick + hitLatency);
 409                     return;
 410                 }
 411                 else {
 412                     //The supplier will be someone else, because we are
 413                     //waiting for the data.  This should cause this cache to
 414                     //be forced to go to the shared state, not the exclusive
 415                     //even though the shared line won't be asserted.  But for
 416                     //now we will just invlidate ourselves and allow the other
 417                     //cache to go into the exclusive state.  @todo Make it so
 418                     //a read to a pending read doesn't invalidate.  @todo Make
 419                     //it so that a read to a pending read can't be exclusive
 420                     //now.
 421
 422                     //Set the address so find match works
 423                     //panic("Don't have invalidates yet\n");
 424                     invalidatePkt->addrOverride(pkt->getAddr());
 425
 426                     //Append the invalidate on
 427                     missQueue->addTarget(mshr,invalidatePkt);
 428                     DPRINTF(Cache, "Appending Invalidate to addr: %x\n",
 429                             pkt->getAddr());
 430                     return;
 431                 }
 432             }
 433         }
 434         //We also need to check the writeback buffers and handle those
 435         std::vector<MSHR *> writebacks;
 436         if (missQueue->findWrites(blk_addr, writebacks)) {
 437             DPRINTF(Cache, "Snoop hit in writeback to addr: %x\n",
 438                     pkt->getAddr());
 439
 440             //Look through writebacks for any non-uncachable writes, use that
 441             for (int i=0; i<writebacks.size(); i++) {
 442                 mshr = writebacks[i];
 443
 444                 if (!mshr->pkt->req->isUncacheable()) {
 445                     if (pkt->isRead()) {
 446                         //Only Upgrades don't get here
 447                         //Supply the data
 448                         assert(!(pkt->flags & SATISFIED));
 449                         pkt->flags |= SATISFIED;
 450
 451                         //If we are in an exclusive protocol, make it ask again
 452                         //to get write permissions (upgrade), signal shared
 453                         pkt->flags |= SHARED_LINE;
 454
 455                         assert(pkt->isRead());
 456                         Addr offset = pkt->getAddr() & (blkSize - 1);
 457                         assert(offset < blkSize);
 458                         assert(pkt->getSize() <= blkSize);
 459                         assert(offset + pkt->getSize() <=blkSize);
 460                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 461
 462                         respondToSnoop(pkt, curTick + hitLatency);
 463                     }
 464
 465                     if (pkt->isInvalidate()) {
 466                         //This must be an upgrade or other cache will take
 467                         //ownership
 468                         missQueue->markInService(mshr->pkt, mshr);
 469                     }
 470                     return;
 471                 }
 472             }
 473         }
 474     }
 475     CacheBlk::State new_state;
 476     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 477     if (satisfy) {
 478         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 479                 "now supplying data, new state is %i\n",
 480                 pkt->cmdString(), blk_addr, new_state);
 481
 482         tags->handleSnoop(blk, new_state, pkt);
 483         respondToSnoop(pkt, curTick + hitLatency);
 484         return;
 485     }
 486     if (blk)
 487         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 488                 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
 489     tags->handleSnoop(blk, new_state);
 490 }
 491
 492 template<class TagStore, class Buffering, class Coherence>
 493 void
 494 Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
 495 {
 496     //Need to handle the response, if NACKED
 497     if (pkt->flags & NACKED_LINE) {
 498         //Need to mark it as not in service, and retry for bus
 499         assert(0); //Yeah, we saw a NACK come through
 500
 501         //For now this should never get called, we return false when we see a
 502         //NACK instead, by doing this we allow the bus_blocked mechanism to
 503         //handle the retry For now it retrys in just 2 cycles, need to figure
 504         //out how to change that Eventually we will want to also have success
 505         //come in as a parameter Need to make sure that we handle the
 506         //functionality that happens on successufl return of the sendAddr
 507         //function
 508     }
 509 }
 510
 511 template<class TagStore, class Buffering, class Coherence>
 512 void
 513 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 514 {
 515     tags->invalidateBlk(addr);
 516 }
 517
 518
 519 /**
 520  * @todo Fix to not assume write allocate
 521  */
 522 template<class TagStore, class Buffering, class Coherence>
 523 Tick
 524 Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
 525                                            CachePort* otherSidePort)
 526 {
 527 //    MemDebug::cacheProbe(pkt);
 528     if (!pkt->req->isUncacheable()) {
 529         if (pkt->isInvalidate() && !pkt->isRead() && !pkt->isWrite()) {
 530             //Upgrade or Invalidate, satisfy it, don't forward
 531             DPRINTF(Cache, "%s %x ?\n", pkt->cmdString(), pkt->getAddr());
 532             pkt->flags |= SATISFIED;
 533             return 0;
 534         }
 535     }
 536
 537     if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
 538         // Still need to change data in all locations.
 539         otherSidePort->sendFunctional(pkt);
 540         if (pkt->isRead() && pkt->result == Packet::Success)
 541             return 0;
 542     }
 543
 544     PacketList writebacks;
 545     int lat;
 546     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 547
 548     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(),
 549             pkt->getAddr(), (blk) ? "hit" : "miss");
 550
 551
 552     // Need to check for outstanding misses and writes
 553     Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 554
 555     // There can only be one matching outstanding miss.
 556     MSHR* mshr = missQueue->findMSHR(blk_addr);
 557
 558     // There can be many matching outstanding writes.
 559     std::vector<MSHR*> writes;
 560     missQueue->findWrites(blk_addr, writes);
 561
 562     if (!update) {
 563         // Check for data in MSHR and writebuffer.
 564         if (mshr) {
 565             MSHR::TargetList *targets = mshr->getTargetList();
 566             MSHR::TargetList::iterator i = targets->begin();
 567             MSHR::TargetList::iterator end = targets->end();
 568             for (; i != end; ++i) {
 569                 PacketPtr target = *i;
 570                 // If the target contains data, and it overlaps the
 571                 // probed request, need to update data
 572                 if (target->intersect(pkt)) {
 573                     fixPacket(pkt, target);
 574                 }
 575             }
 576         }
 577         for (int i = 0; i < writes.size(); ++i) {
 578             PacketPtr write = writes[i]->pkt;
 579             if (write->intersect(pkt)) {
 580                 fixPacket(pkt, write);
 581             }
 582         }
 583         if (pkt->isRead()
 584             && pkt->result != Packet::Success
 585             && otherSidePort == memSidePort) {
 586             otherSidePort->sendFunctional(pkt);
 587             assert(pkt->result == Packet::Success);
 588         }
 589         return 0;
 590     } else if (!blk && !(pkt->flags & SATISFIED)) {
 591         // update the cache state and statistics
 592         if (mshr || !writes.empty()){
 593             // Can't handle it, return request unsatisfied.
 594             panic("Atomic access ran into outstanding MSHR's or WB's!");
 595         }
 596         if (!pkt->req->isUncacheable()) {
 597                 // Fetch the cache block to fill
 598             BlkType *blk = tags->findBlock(pkt);
 599             Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 600                                                             (blk)? blk->status : 0);
 601
 602             PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 603
 604             busPkt->allocate();
 605
 606             busPkt->time = curTick;
 607
 608             DPRINTF(Cache, "Sending a atomic %s for %x\n",
 609                     busPkt->cmdString(), busPkt->getAddr());
 610
 611             lat = memSidePort->sendAtomic(busPkt);
 612
 613             //Be sure to flip the response to a request for coherence
 614             if (busPkt->needsResponse()) {
 615                 busPkt->makeAtomicResponse();
 616             }
 617
 618 /*              if (!(busPkt->flags & SATISFIED)) {
 619 // blocked at a higher level, just return
 620 return 0;
 621 }
 622
 623 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 624
 625             CacheBlk::State old_state = (blk) ? blk->status : 0;
 626             CacheBlk::State new_state =
 627                 coherence->getNewState(busPkt, old_state);
 628             DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
 629                     busPkt->cmdString(), busPkt->getAddr(), old_state);
 630             if (old_state != new_state)
 631                 DPRINTF(Cache, "Block for blk addr %x moving from state "
 632                         "%i to %i\n", busPkt->getAddr(), old_state, new_state);
 633
 634             tags->handleFill(blk, busPkt, new_state, writebacks, pkt);
 635             //Free the packet
 636             delete busPkt;
 637
 638             // Handle writebacks if needed
 639             while (!writebacks.empty()){
 640                 PacketPtr wbPkt = writebacks.front();
 641                 memSidePort->sendAtomic(wbPkt);
 642                 writebacks.pop_front();
 643                 delete wbPkt;
 644             }
 645                 return lat + hitLatency;
 646         } else {
 647             return memSidePort->sendAtomic(pkt);
 648         }
 649     } else {
 650         if (blk) {
 651             // There was a cache hit.
 652             // Handle writebacks if needed
 653             while (!writebacks.empty()){
 654                 memSidePort->sendAtomic(writebacks.front());
 655                 writebacks.pop_front();
 656             }
 657
 658             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 659         }
 660
 661         return hitLatency;
 662     }
 663
 664     return 0;
 665 }
 666
 667 template<class TagStore, class Buffering, class Coherence>
 668 Tick
 669 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 670 {
 671     //Send a atomic (false) invalidate up if the protocol calls for it
 672     coherence->propogateInvalidate(pkt, false);
 673
 674     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 675     BlkType *blk = tags->findBlock(pkt);
 676     MSHR *mshr = missQueue->findMSHR(blk_addr);
 677     CacheBlk::State new_state = 0;
 678     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 679     if (satisfy) {
 680         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 681                 "now supplying data, new state is %i\n",
 682                 pkt->cmdString(), blk_addr, new_state);
 683
 684             tags->handleSnoop(blk, new_state, pkt);
 685             return hitLatency;
 686     }
 687     if (blk)
 688         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 689                 "new state is %i\n",
 690                     pkt->cmdString(), blk_addr, new_state);
 691     tags->handleSnoop(blk, new_state);
 692     return 0;
 693 }
 694