src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_events.hh" // for SimExitEvent
  55
  56 using namespace std;
  57
  58 template<class TagStore, class Buffering, class Coherence>
  59 bool
  60 Cache<TagStore,Buffering,Coherence>::
  61 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  62 {
  63     if (isCpuSide)
  64     {
  65         access(pkt);
  66     }
  67     else
  68     {
  69         if (pkt->isResponse())
  70             handleResponse(pkt);
  71         else
  72             snoop(pkt);
  73     }
  74     return true; //Deal with blocking....
  75 }
  76
  77 template<class TagStore, class Buffering, class Coherence>
  78 Tick
  79 Cache<TagStore,Buffering,Coherence>::
  80 doAtomicAccess(Packet *pkt, bool isCpuSide)
  81 {
  82     if (isCpuSide)
  83     {
  84         probe(pkt, true);
  85         //TEMP ALWAYS SUCCES FOR NOW
  86         pkt->result = Packet::Success;
  87     }
  88     else
  89     {
  90         if (pkt->isResponse())
  91             handleResponse(pkt);
  92         else
  93             snoopProbe(pkt, true);
  94     }
  95     //Fix this timing info
  96     return hitLatency;
  97 }
  98
  99 template<class TagStore, class Buffering, class Coherence>
 100 void
 101 Cache<TagStore,Buffering,Coherence>::
 102 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 103 {
 104     if (isCpuSide)
 105     {
 106         //TEMP USE CPU?THREAD 0 0
 107         pkt->req->setThreadContext(0,0);
 108         probe(pkt, true);
 109         //TEMP ALWAYS SUCCESFUL FOR NOW
 110         pkt->result = Packet::Success;
 111     }
 112     else
 113     {
 114         if (pkt->isResponse())
 115             handleResponse(pkt);
 116         else
 117             snoopProbe(pkt, true);
 118     }
 119 }
 120
 121 template<class TagStore, class Buffering, class Coherence>
 122 void
 123 Cache<TagStore,Buffering,Coherence>::
 124 recvStatusChange(Port::Status status, bool isCpuSide)
 125 {
 126
 127 }
 128
 129
 130 template<class TagStore, class Buffering, class Coherence>
 131 Cache<TagStore,Buffering,Coherence>::
 132 Cache(const std::string &_name,
 133       Cache<TagStore,Buffering,Coherence>::Params &params)
 134     : BaseCache(_name, params.baseParams),
 135       prefetchAccess(params.prefetchAccess),
 136       tags(params.tags), missQueue(params.missQueue),
 137       coherence(params.coherence), prefetcher(params.prefetcher),
 138       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
 139 {
 140 //FIX BUS POINTERS
 141 //    if (params.in == NULL) {
 142         topLevelCache = true;
 143 //    }
 144 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
 145         tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
 146     tags->setPrefetcher(prefetcher);
 147     missQueue->setCache(this);
 148     missQueue->setPrefetcher(prefetcher);
 149     coherence->setCache(this);
 150     prefetcher->setCache(this);
 151     prefetcher->setTags(tags);
 152     prefetcher->setBuffer(missQueue);
 153 #if 0
 154     invalidatePkt = new Packet;
 155     invalidatePkt->cmd = Packet::InvalidateReq;
 156 #endif
 157 }
 158
 159 template<class TagStore, class Buffering, class Coherence>
 160 void
 161 Cache<TagStore,Buffering,Coherence>::regStats()
 162 {
 163     BaseCache::regStats();
 164     tags->regStats(name());
 165     missQueue->regStats(name());
 166     coherence->regStats(name());
 167     prefetcher->regStats(name());
 168 }
 169
 170 template<class TagStore, class Buffering, class Coherence>
 171 bool
 172 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 173 {
 174 //@todo Add back in MemDebug Calls
 175 //    MemDebug::cacheAccess(pkt);
 176     BlkType *blk = NULL;
 177     PacketList writebacks;
 178     int size = blkSize;
 179     int lat = hitLatency;
 180     if (prefetchAccess) {
 181         //We are determining prefetches on access stream, call prefetcher
 182         prefetcher->handleMiss(pkt, curTick);
 183     }
 184     if (!pkt->req->isUncacheable()) {
 185         if (pkt->isInvalidate() && !pkt->isRead()
 186             && !pkt->isWrite()) {
 187             //Upgrade or Invalidate
 188             //Look into what happens if two slave caches on bus
 189             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 190                     pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
 191                     pkt->getAddr() & ~((Addr)blkSize - 1));
 192
 193             //@todo Should this return latency have the hit latency in it?
 194 //          respond(pkt,curTick+lat);
 195             pkt->flags |= SATISFIED;
 196 //            return MA_HIT; //@todo, return values
 197             return true;
 198         }
 199         blk = tags->handleAccess(pkt, lat, writebacks);
 200     } else {
 201         size = pkt->getSize();
 202     }
 203     // If this is a block size write/hint (WH64) allocate the block here
 204     // if the coherence protocol allows it.
 205     /** @todo make the fast write alloc (wh64) work with coherence. */
 206     /** @todo Do we want to do fast writes for writebacks as well? */
 207     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 208         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 209         // not outstanding misses, can do this
 210         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr(), pkt->req->getAsid());
 211         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 212             if (outstanding_miss) {
 213                 warn("WriteInv doing a fastallocate"
 214                      "with an outstanding miss to the same address\n");
 215             }
 216             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 217                                    writebacks);
 218             ++fastWrites;
 219         }
 220     }
 221     while (!writebacks.empty()) {
 222         missQueue->doWriteback(writebacks.front());
 223         writebacks.pop_front();
 224     }
 225     DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
 226             pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 227             pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
 228     if (blk) {
 229         // Hit
 230         hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 231         // clear dirty bit if write through
 232         if (pkt->needsResponse())
 233             respond(pkt, curTick+lat);
 234 //      return MA_HIT;
 235         return true;
 236     }
 237
 238     // Miss
 239     if (!pkt->req->isUncacheable()) {
 240         misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 241         /** @todo Move miss count code into BaseCache */
 242         if (missCount) {
 243             --missCount;
 244             if (missCount == 0)
 245                 new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
 246         }
 247     }
 248     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 249 //    return MA_CACHE_MISS;
 250     return true;
 251 }
 252
 253
 254 template<class TagStore, class Buffering, class Coherence>
 255 Packet *
 256 Cache<TagStore,Buffering,Coherence>::getPacket()
 257 {
 258     Packet * pkt = missQueue->getPacket();
 259     if (pkt) {
 260         if (!pkt->req->isUncacheable()) {
 261             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
 262             BlkType *blk = tags->findBlock(pkt);
 263             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 264                                               (blk)? blk->status : 0);
 265             missQueue->setBusCmd(pkt, cmd);
 266         }
 267     }
 268
 269     assert(!doMasterRequest() || missQueue->havePending());
 270     assert(!pkt || pkt->time <= curTick);
 271     return pkt;
 272 }
 273
 274 template<class TagStore, class Buffering, class Coherence>
 275 void
 276 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
 277 {
 278     if (success) {
 279         missQueue->markInService(pkt);
 280           //Temp Hack for UPGRADES
 281           if (pkt->cmd == Packet::UpgradeReq) {
 282               handleResponse(pkt);
 283           }
 284     } else if (pkt && !pkt->req->isUncacheable()) {
 285         missQueue->restoreOrigCmd(pkt);
 286     }
 287 }
 288
 289 template<class TagStore, class Buffering, class Coherence>
 290 void
 291 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 292 {
 293     BlkType *blk = NULL;
 294     if (pkt->senderState) {
 295 //      MemDebug::cacheResponse(pkt);
 296         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 297                 pkt->getAddr() & (((ULL(1))<<48)-1));
 298
 299         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 300             blk = tags->findBlock(pkt);
 301             CacheBlk::State old_state = (blk) ? blk->status : 0;
 302             PacketList writebacks;
 303             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 304                                    coherence->getNewState(pkt,old_state),
 305                                    writebacks);
 306             while (!writebacks.empty()) {
 307                     missQueue->doWriteback(writebacks.front());
 308             }
 309         }
 310         missQueue->handleResponse(pkt, curTick + hitLatency);
 311     }
 312 }
 313
 314 template<class TagStore, class Buffering, class Coherence>
 315 void
 316 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr, int asid)
 317 {
 318     // Need to temporarily move this blk into MSHRs
 319     MSHR *mshr = missQueue->allocateTargetList(addr, asid);
 320     int lat;
 321     PacketList dummy;
 322     // Read the data into the mshr
 323     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 324     assert(dummy.empty());
 325     assert(mshr->pkt->flags & SATISFIED);
 326     // can overload order since it isn't used on non pending blocks
 327     mshr->order = blk->status;
 328     // temporarily remove the block from the cache.
 329     tags->invalidateBlk(addr, asid);
 330 }
 331
 332 template<class TagStore, class Buffering, class Coherence>
 333 void
 334 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 335 {
 336     // Need to temporarily move this blk into MSHRs
 337     assert(mshr->pkt->cmd == Packet::ReadReq);
 338     int lat;
 339     PacketList dummy;
 340     // Read the data into the mshr
 341     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 342     assert(dummy.empty());
 343     assert(mshr->pkt->flags & SATISFIED);
 344     // can overload order since it isn't used on non pending blocks
 345     mshr->order = blk->status;
 346     // temporarily remove the block from the cache.
 347     tags->invalidateBlk(mshr->pkt->getAddr(), mshr->pkt->req->getAsid());
 348 }
 349
 350
 351 template<class TagStore, class Buffering, class Coherence>
 352 Packet *
 353 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 354 {
 355     return coherence->getPacket();
 356 }
 357
 358
 359 template<class TagStore, class Buffering, class Coherence>
 360 void
 361 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 362 {
 363
 364     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 365     BlkType *blk = tags->findBlock(pkt);
 366     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 367     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 368         //If we find an mshr, and it is in service, we need to NACK or invalidate
 369         if (mshr) {
 370             if (mshr->inService) {
 371                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 372                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 373                     //If the outstanding request was an invalidate (upgrade,readex,..)
 374                     //Then we need to ACK the request until we get the data
 375                     //Also NACK if the outstanding request is not a cachefill (writeback)
 376                     pkt->flags |= NACKED_LINE;
 377                     return;
 378                 }
 379                 else {
 380                     //The supplier will be someone else, because we are waiting for
 381                     //the data.  This should cause this cache to be forced to go to
 382                     //the shared state, not the exclusive even though the shared line
 383                     //won't be asserted.  But for now we will just invlidate ourselves
 384                     //and allow the other cache to go into the exclusive state.
 385                     //@todo Make it so a read to a pending read doesn't invalidate.
 386                     //@todo Make it so that a read to a pending read can't be exclusive now.
 387
 388                     //Set the address so find match works
 389                     invalidatePkt->addrOverride(pkt->getAddr());
 390
 391                     //Append the invalidate on
 392                     missQueue->addTarget(mshr,invalidatePkt);
 393                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 394                     return;
 395                 }
 396             }
 397         }
 398         //We also need to check the writeback buffers and handle those
 399         std::vector<MSHR *> writebacks;
 400         if (missQueue->findWrites(blk_addr, pkt->req->getAsid(), writebacks)) {
 401             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 402
 403             //Look through writebacks for any non-uncachable writes, use that
 404             for (int i=0; i<writebacks.size(); i++) {
 405                 mshr = writebacks[i];
 406
 407                 if (!mshr->pkt->req->isUncacheable()) {
 408                     if (pkt->isRead()) {
 409                         //Only Upgrades don't get here
 410                         //Supply the data
 411                         pkt->flags |= SATISFIED;
 412
 413                         //If we are in an exclusive protocol, make it ask again
 414                         //to get write permissions (upgrade), signal shared
 415                         pkt->flags |= SHARED_LINE;
 416
 417                         assert(pkt->isRead());
 418                         Addr offset = pkt->getAddr() & ~(blkSize - 1);
 419                         assert(offset < blkSize);
 420                         assert(pkt->getSize() <= blkSize);
 421                         assert(offset + pkt->getSize() <=blkSize);
 422                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 423
 424                         respondToSnoop(pkt);
 425                     }
 426
 427                     if (pkt->isInvalidate()) {
 428                         //This must be an upgrade or other cache will take ownership
 429                         missQueue->markInService(mshr->pkt);
 430                     }
 431                     return;
 432                 }
 433             }
 434         }
 435     }
 436     CacheBlk::State new_state;
 437     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 438     if (satisfy) {
 439         tags->handleSnoop(blk, new_state, pkt);
 440         respondToSnoop(pkt);
 441         return;
 442     }
 443     tags->handleSnoop(blk, new_state);
 444 }
 445
 446 template<class TagStore, class Buffering, class Coherence>
 447 void
 448 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 449 {
 450     //Need to handle the response, if NACKED
 451     if (pkt->flags & NACKED_LINE) {
 452         //Need to mark it as not in service, and retry for bus
 453         assert(0); //Yeah, we saw a NACK come through
 454
 455         //For now this should never get called, we return false when we see a NACK
 456         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 457         //For now it retrys in just 2 cycles, need to figure out how to change that
 458         //Eventually we will want to also have success come in as a parameter
 459         //Need to make sure that we handle the functionality that happens on successufl
 460         //return of the sendAddr function
 461     }
 462 }
 463
 464 template<class TagStore, class Buffering, class Coherence>
 465 void
 466 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr, int asid)
 467 {
 468     tags->invalidateBlk(addr,asid);
 469 }
 470
 471
 472 /**
 473  * @todo Fix to not assume write allocate
 474  */
 475 template<class TagStore, class Buffering, class Coherence>
 476 Tick
 477 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 478 {
 479 //    MemDebug::cacheProbe(pkt);
 480     if (!pkt->req->isUncacheable()) {
 481         if (pkt->isInvalidate() && !pkt->isRead()
 482             && !pkt->isWrite()) {
 483             //Upgrade or Invalidate, satisfy it, don't forward
 484             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 485                     pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
 486                     pkt->getAddr() & ~((Addr)blkSize - 1));
 487             pkt->flags |= SATISFIED;
 488             return 0;
 489         }
 490     }
 491
 492     PacketList writebacks;
 493     int lat;
 494     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 495
 496     if (!blk) {
 497         // Need to check for outstanding misses and writes
 498         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 499
 500         // There can only be one matching outstanding miss.
 501         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 502
 503         // There can be many matching outstanding writes.
 504         vector<MSHR*> writes;
 505         missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
 506
 507         if (!update) {
 508             memSidePort->sendFunctional(pkt);
 509             // Check for data in MSHR and writebuffer.
 510             if (mshr) {
 511                 warn("Found outstanding miss on an non-update probe");
 512                 MSHR::TargetList *targets = mshr->getTargetList();
 513                 MSHR::TargetList::iterator i = targets->begin();
 514                 MSHR::TargetList::iterator end = targets->end();
 515                 for (; i != end; ++i) {
 516                     Packet * target = *i;
 517                     // If the target contains data, and it overlaps the
 518                     // probed request, need to update data
 519                     if (target->isWrite() && target->intersect(pkt)) {
 520                         uint8_t* pkt_data;
 521                         uint8_t* write_data;
 522                         int data_size;
 523                         if (target->getAddr() < pkt->getAddr()) {
 524                             int offset = pkt->getAddr() - target->getAddr();
 525                             pkt_data = pkt->getPtr<uint8_t>();
 526                             write_data = target->getPtr<uint8_t>() + offset;
 527                             data_size = target->getSize() - offset;
 528                             assert(data_size > 0);
 529                             if (data_size > pkt->getSize())
 530                                 data_size = pkt->getSize();
 531                         } else {
 532                             int offset = target->getAddr() - pkt->getAddr();
 533                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 534                             write_data = target->getPtr<uint8_t>();
 535                             data_size = pkt->getSize() - offset;
 536                             assert(data_size > pkt->getSize());
 537                             if (data_size > target->getSize())
 538                                 data_size = target->getSize();
 539                         }
 540
 541                         if (pkt->isWrite()) {
 542                             memcpy(pkt_data, write_data, data_size);
 543                         } else {
 544                             memcpy(write_data, pkt_data, data_size);
 545                         }
 546                     }
 547                 }
 548             }
 549             for (int i = 0; i < writes.size(); ++i) {
 550                 Packet * write = writes[i]->pkt;
 551                 if (write->intersect(pkt)) {
 552                     warn("Found outstanding write on an non-update probe");
 553                     uint8_t* pkt_data;
 554                     uint8_t* write_data;
 555                     int data_size;
 556                     if (write->getAddr() < pkt->getAddr()) {
 557                         int offset = pkt->getAddr() - write->getAddr();
 558                         pkt_data = pkt->getPtr<uint8_t>();
 559                         write_data = write->getPtr<uint8_t>() + offset;
 560                         data_size = write->getSize() - offset;
 561                         assert(data_size > 0);
 562                         if (data_size > pkt->getSize())
 563                             data_size = pkt->getSize();
 564                     } else {
 565                         int offset = write->getAddr() - pkt->getAddr();
 566                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 567                         write_data = write->getPtr<uint8_t>();
 568                         data_size = pkt->getSize() - offset;
 569                         assert(data_size > pkt->getSize());
 570                         if (data_size > write->getSize())
 571                             data_size = write->getSize();
 572                     }
 573
 574                     if (pkt->isWrite()) {
 575                         memcpy(pkt_data, write_data, data_size);
 576                     } else {
 577                         memcpy(write_data, pkt_data, data_size);
 578                     }
 579
 580                 }
 581             }
 582             return 0;
 583         } else {
 584             // update the cache state and statistics
 585             if (mshr || !writes.empty()){
 586                 // Can't handle it, return pktuest unsatisfied.
 587                 return 0;
 588             }
 589             if (!pkt->req->isUncacheable()) {
 590                 // Fetch the cache block to fill
 591                 BlkType *blk = tags->findBlock(pkt);
 592                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 593                                                    (blk)? blk->status : 0);
 594
 595                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 596
 597                 busPkt->allocate();
 598
 599                 busPkt->time = curTick;
 600
 601                 lat = memSidePort->sendAtomic(busPkt);
 602
 603 /*              if (!(busPkt->flags & SATISFIED)) {
 604                     // blocked at a higher level, just return
 605                     return 0;
 606                 }
 607
 608 */              misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 609
 610                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 611                 tags->handleFill(blk, busPkt,
 612                                  coherence->getNewState(busPkt, old_state),
 613                                  writebacks, pkt);
 614                 // Handle writebacks if needed
 615                 while (!writebacks.empty()){
 616                     memSidePort->sendAtomic(writebacks.front());
 617                     writebacks.pop_front();
 618                 }
 619                 return lat + hitLatency;
 620             } else {
 621                 return memSidePort->sendAtomic(pkt);
 622             }
 623         }
 624     } else {
 625         // There was a cache hit.
 626         // Handle writebacks if needed
 627         while (!writebacks.empty()){
 628             memSidePort->sendAtomic(writebacks.front());
 629             writebacks.pop_front();
 630         }
 631
 632         if (update) {
 633             hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 634         } else if (pkt->isWrite()) {
 635             // Still need to change data in all locations.
 636             return memSidePort->sendAtomic(pkt);
 637         }
 638         return curTick + lat;
 639     }
 640     fatal("Probe not handled.\n");
 641     return 0;
 642 }
 643
 644 template<class TagStore, class Buffering, class Coherence>
 645 Tick
 646 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
 647 {
 648     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 649     BlkType *blk = tags->findBlock(pkt);
 650     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 651     CacheBlk::State new_state = 0;
 652     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 653     if (satisfy) {
 654         tags->handleSnoop(blk, new_state, pkt);
 655         return hitLatency;
 656     }
 657     tags->handleSnoop(blk, new_state);
 658     return 0;
 659 }
 660